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toshiba toshiba corporation 1 tlcs-90 series TMP90CM36 the information contained here is subject to change without notice. the information contained herein is presented only as guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. these toshiba products are intended for usage in general electronic equipments (of?e equipment, communication equipment, measuring equipment, domestic electri?ation, etc.) please make sure that you consult with us before you use these toshiba products in equip- ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traf? signal, combustion control, all types of safety devices, etc.). toshiba cannot accept liability to any damage which may occur in case these toshiba products were used in the mentioned equipments without prior consultation with toshiba. cmos 8?it microcontroller TMP90CM36f/TMP90CM36t 1. outline and characteristics the TMP90CM36 is a high-speed, high performance 8-bit microcontroller developed for application in the control of various devices. the TMP90CM36, cmos 8-bit microcontroller, integrates an 8-bit cpu, rom, ram, a/d converter, d/a converter, multi-func- tion timer/event counter, general-purpose serial interface, signal measure circuit, timing pulse generation circuit and pwm output in a single chip, and with which external program memory and data memory can be extended up to 31kb. the TMP90CM36f is a device with an 80-pin ?t pack- age. the TMP90CM36t is a device with an 84-pin qf (plcc) package. the following are the features of the TMP90CM36: (1) highly ef?ient instruction set: 167 basic instructions division and multiplication instructions, 16-bit opera- tion instructions and bit operation instructions (2) minimum instruction executing time: 250ns (at 16mhz oscillation frequency) (3) built-in rom: 32k bytes (4) built-in ram: 1k bytes (5) memory extension capability external program memory: 31k bytes external data memory: 31k bytes (6) interrupt functions: 18 internal, 5 external (7) 8-bit a/d converter (8 channels) (8) 8-bit d/a converter (2 channels) (9) 12-bit d/a conversion (pulse width change of tone) output (2 channels) (10) general-purpose serial interface mode (3 channels) with asynchronous mode and i/o interface mode (1 channel) with synchronous mode (1 channel) i/o interface mode (1 channels) (11) timer function (1) 20-bit time base counter (2) 24-bit capture with 4 step fifo (3) 24-bit timing pulse generation circuit (2 channels) (comparator data 16-bit + timing output 8-bit) x 4 step fifo (4) 16-bit timer/event counter (1 channel) ----- built-in 2 capture register and 2 comparator (5) 8-bit timer (4 channels) ----- built-in 1 comparator in each channel (6) watchdog timer function (wdtout pin having) (12) i/o ports: max64 pins (13) hdma function (2 channels) ----- 1 byte transmission: 1.75 m s (@16.0mhz) (14) software standby function ----- run, stop, idle modes hardware standby function ----- stop mode
2 toshiba corporation TMP90CM36 figure 1. TMP90CM36 block diagram
toshiba corporation 3 TMP90CM36 2. pin assignment and functions the assignment of input/output pins for TMP90CM36, their name and outline functions are described below. 2.1 pin layout diagram figure 2.1 (1) shows the pin assignment of TMP90CM36f. figure 2.1 (1). pin assignments (flat package)
4 toshiba corporation TMP90CM36 figure 2.1 (2) shows the pin assignment of TMP90CM36t. figure 2.1 (2). pin assignments (qfj (plcc) package)
toshiba corporation 5 TMP90CM36 2.2 pin names and functions the names of input/output pins and their functions are described below. table 2.2 shows the input/output pin names and functions. table 2.2. pin names and functions (1/4)
6 toshiba corporation TMP90CM36 table 2.2. pin names and functions (2/4)
toshiba corporation 7 TMP90CM36 table 2.2. pin names and functions (3/4)
8 toshiba corporation TMP90CM36 table 2.2. pin names and functions (4/4)
toshiba corporation 9 TMP90CM36 3. operation this section explains the functions and basic operations of the TMP90CM36 in blocks. 3.1 cpu the TMP90CM36 has a built-in high performance 8 bit cpu. for the operation of the cpu, see the book tlcs 90 series cpu core architecture. this section explains the cpu functions unique to the TMP90CM36 that are not explained in that book. 3.1.1 reset figure 3.1 (1) shows the basic timing of reset. to reset the TMP90CM36, it is required that the power supply voltage is within operating range, the internal oscillator is stably functioning, and reset input be kept at ??for at least 10 system clocks (10 states: 2 microseconds with 10mhz system clock) when a reset is accepted, among i/o common ports, port 0 (address data bus a0 - a7), port 1 (address data bus a8 - a15) and port 2 are set to input status (with high impedance). output ports p30 (rd ) and p31 (wr ) and clk are set to ?? and ale (p83) is cleared to ?? cpu registers and external memory are not changed. however, program counter pc and interrupt enable/disable ?g iff are cleared to ?? the a register becomes unde?ed. when the reset is released, instruction execution starts from address 0000h. figure 3.1 (1). reset timing of TMP90CM36
10 toshiba corporation TMP90CM36 3.1.2 exf (exchange flag) the exchange ?g exf is inverted when the exx instruction is executed to exchange data between the TMP90CM36 main registers and auxiliary registers. this ?g is assigned to bit 7 at memory address ffe1h. 3.1.3 wait control for the TMP90CM36, a wait control register (w aitc) is assigned to bits 4 and 5 at memory address ffb4h.
toshiba corporation 11 TMP90CM36 3.2 memory map the TMP90CM36 can provide a maximum 64k byte program memory and data memory. the program and data memories may be allocated to the addresses 0000h ~ ffffh. (1) built-in rom the TMP90CM36 has an internal 32k byte rom. this rom is located at addresses 0000h ~ 7fffh. pro- gram execution starts from address 000h after a reset operation. addresses 0008h ~ 0078h in the internal rom area are used as the interrupt processing entry area. (2) built-in ram the TMP90CM36 contains a 1k byte built-in ram which is allocated to the addresses fba0h ~ ff9fh. the cpu can also access some portions of the ram (160 byte area ff00h ~ ff9fh) using short instruction codes in the direct addressing mode. (3) built-in i/o the TMP90CM36 uses 96 bytes of the address space as a built-in i/o area. the area is allocated to the addresses ffa0h ~ ffffh. the cpu can access the built-in i/o using short instruction codes in the direct addressing mode. figure 3.2 shows the memory map and the access ranges of the cpu for each addressing mode. figure 3.2. memory map
12 toshiba corporation TMP90CM36 3.3 interrupt functions the TMP90CM36 has a general-purpose interrupt process- ing routine for responding to both internal and external inter- rupt request, and a high-speed micro dma (hdma) processing mode in which the cpu automatically transfers data. immediately after a reset is released, all responses to interrupt requests are set to the general-purpose interrupt processing mode. the high-speed dma processing mode can be set by loading a vector value to the dmav 0/1 register. figure 3.3 (1) shows the interrupt response ?w. figure 3.3 (1). interrupt response flow when an interrupt request is generated, this is reported to the cpu via the built-in interrupt controller. if the request is for a non-maskable interrupt or an enabled maskable interrupt, the cpu starts interrupt processing. if for a disabled maskable interrupt, the request is ignored and not received. if the interrupt is received, the cpu ?st reads the interrupt vector from the built-in interrupt controller to determine the source of the interrupt request. next, a check is made as to whether this request is for general-purpose interrupt processing, micro dma processing or high-speed dma (hdma) processing, and then the corre- sponding pr ocessing is performed. the interrupt vector is read in an internal operation cycle so the bus cycle becomes a dummy cycle.
toshiba corporation 13 TMP90CM36 3.3.1 general-purpose interrupt processing figure 3.3 (2) shows the general-purpose interrupt processing ?w. the cpu ?st saves the contents of the program counter pc and register af (including the interrupt enable/disable ?g iff immediately before an interrupt) to the stack and then resets the interrupt enable/disable ?g iff to ??(interrupt disable). finally, the interrupt vector contents [v] are transferred to the program counter and a jump is made to the interrupt processing pr ogram. there is a 20-state overhead from the time when the interrupt is received until the jump is made to the interrupt processing program. figure 3.3 (2). general-purpose interrupt processing flow interrupt processing program is ended with the reti instruction for both maskable and non-maskable interrupts. executing this instruction restores the program counter pc and register af contents from the stack. (resets the interrupt enable/disable ?g immediately before an interrupt.) when the cpu reads the interrupt vector, the interrupt request source con?ms that the interrupt has been received and then clears the interrupt request. non-maskable interrupts cannot be disabled by program. maskable interrupts, how- ever, can be enabled and disabled by program. bit 5 of cpu reg- ister f is an interrupt enable/disable ?p?p (iff). interrupts are enabled by setting this bit to ??with the ei (interrupt enable) instruction and disabled by resetting this bit to ??with the di (interrupt disable) instruction. iff is reset to ??by resetting and when an interrupt is received (including non-maskable interrupts). the ei instruction is actually executed after the next instruction is executed. table 3.3 (1) shows the interrupt sources.
14 toshiba corporation TMP90CM36 table 3.3 (1) interrupt sources the ?riority sequence?shown in table 3.3 (1) indicates the sequence in which interrupt sources are received by the cpu when multiple interrupt requests are generated simulta- neously. for example, if interrupt requests with the priority sequences 4 and 5 are generated simultaneously, the cpu will receive the interrupt request with priority sequence 4 ?st. when processing of the interrupt with priority sequence 4 is ended with the reti instruction, the cpu will then receive the interrupt with priority sequence 5. if the interrupt processing program for the priority sequence 4 interrupt is interrupted by executing the ei instruction, the cpu will receive the priority sequence 5 interrupt request. when multiple interrupt requests are generated simultaneously, the built-in interrupt controller only determines the priority sequence of the interrupt sources received by the cpu. there is no function to compare the priority sequence of the interrupt currently being processed and the interrupt currently being requested. another interrupt can be enabled while another interrupt is being processed by resetting the interrupt enable/disable ?g iff to enable.
toshiba corporation 15 TMP90CM36 3.3.2 high-speed micro dma processing the TMP90CM36 has two built-in dma channels called hdma. hdma has three times the processing capacity of m dma and is used for high-speed data transfers. hdma execution time (decrease the value of transfer number and the value is not ??data) is 14 states, regardless of whether the 1-byte transfer mode or 2-byte transfer mode is used. hdma and micro dma (the TMP90CM36 has not the micro dma) transfer speeds. table 3.3 (3) shows the high-speed micro. table 3.3 (3) transfer speeds table 3.3 (4) shows the dhma functions (1) hdma setting registers the following describes the registers required for hdma operation.
16 toshiba corporation TMP90CM36
toshiba corporation 17 TMP90CM36 (2) register loading note: it is ineffective to set decrement for a destination address when a source address being increment; and to set increment for a destination address when a source address being decrement. (3) hdma start hdma can be started by any of the following TMP90CM36 maskable interrupt sources (a) internal start factors swi (software) all internal i/o interrupts assign starting of hdma channel 0 or channel 1 to the int0 - int3 external interrupts, connect any of the bits of ports 0 - 8 (output mode) externally to int0 - int3 to generate a start interrupt. (b) external start factors nmi pin int0 ~ 3 pin
18 toshiba corporation TMP90CM36 (4) hdma channel 0 and channel 1 priority sequence the channel where an interrupt is generated ?st has priority. note: hdma, regardless of an interrupt enable ?g, compares the vector and the values of the dma v0/1 register. if they match in ei mode, the hdma starts. do not write the vector value of the non- maskable interrupt to the dma v0/1 register. if doing so, the hdma does not operate normally. to stop the hdma from being started, set di mode before generating the interrupt to start the hdma, or set the dma v0/1 register to 00h. (5) hdma operation flow figure 3.3 (6). hdma operation flow
toshiba corporation 19 TMP90CM36 (6) hdma operation timing
20 toshiba corporation TMP90CM36
toshiba corporation 21 TMP90CM36 3.3.3 interrupt controller figure 3.3 (9) shows an abbreviated interrupt circuit diagram. the left half of this diagram shows the interrupt controller and the right half shows the cpu interrupt request signal circuit and hold release circuit. the interrupt controller has an interrupt request ?p?p and interrupt enable/disable ?g for each interrupt channel (total: 23 channels), and a micro dma enable/disable ?g. the interrupt request ?p?p latches interrupt requests that arrive from the periphery. this ?p?p is reset to ??when there is a reset, when the cpu receives an interrupt and reads the vector of that interrupt channel, and when an instruction that clears the interrupt request (writes ?ector value/8?to memory address ffe0h) for that channel is executed. ld (0ffe0h), 60h/8 for example, when ld (0ffe0h), 60h/8 is executed, the interrupt request ?p?p for the interrupt channel [intt1] with the vector value 38h is reset to ??(to clear the ?p?p, also write to address ffc9h when the interrupt request ?g is assigned to ffe1h and ffe2h). table 3.3 (5) shows the ?nterrupt vector value/8?values. the status of the interrupt request ?p?p can be determined by reading memory address ffc9h, ffcah or ffcbh. ?? means no interrupt request and ??means an interrupt request. figure 3.3 (8) shows the bit layout when the interrupt request ?p?p is read.
22 toshiba corporation TMP90CM36 table 3.3 (4) interrupt vector value/8 values figure 3.3 (5). interrupt request flip?p read (1/2)
toshiba corporation 23 TMP90CM36 figure 3.3 (6). interrupt request flip?p read (2/2)
24 toshiba corporation TMP90CM36 figure 3.3 (7). interrupt controller block
toshiba corporation 25 TMP90CM36 the interrupt enable/disable ?gs for each interrupt request channel are assigned to memory addresses ffe3h - ffe5h. interrupts are enabled for a channel by setting the ?g to ?? the ?gs are reset to ??by reseting. interrupt common terminal mode how to set int0 p81 level inte2 = 0 rise edge inte2 = 1 int1 p53 rise edge t4mod = 0, 0 or 0, 1 or 1, 1 fall edge t4mod = 1, 0 int2 p54 rise edge int2 p56 rise edge for the pulse width for external interrupt, refer to ?.7 interrupt operation? be careful that the following ?e are exceptional circuits.
26 toshiba corporation TMP90CM36 int0 level mode as the int0 is not an edge type interrupt, the interrupt request flipflop is cancelled, and thus an interrupt request from peripheral devices passes through s input of the flipflop to become q output. when the mode is changed over (from edge type to level type), the previous interrupt request flag will be cleared automatically. when the mode is changed from level to edge, the interrupt request flag set in the level mode is not cleared. thus, use the following sequence to clear the interrupt request flag. di set 6, (0ffe5h): switch the mode from level to edge ld (0ffe0h), feh: clear interrupt request flag ei intrx1, intrx2 the interrupt request flipflop cannot be cleared only by reset operation or reading the serial channel receiving buffer, and cannot be cleared by an instruction.
toshiba corporation 27 TMP90CM36 figure 3.3 (8). interrupt enable flags
28 toshiba corporation TMP90CM36 figure 3.3 (9). interrupt processing flow chart
toshiba corporation 29 TMP90CM36 3.4 standby functions when a halt instruction is executed, TMP90CM36 enters the run, idle1 or stop mode according to the contents of the halt mode setting register. the features are shown below. (1) run: only the cpu halts, power consumption remains unchanged. (2) idle: only the internal oscillators operate, while all other internal circuits halt. power consump- tion is 1/10 or less than that during normal operation. (3) stop: all internal circuits halt, including the internal oscillator. power consumption is extremely reduced. the halt mode setting register wdmod is assigned to bits 2 and 3 memory address ffech in the built-in i/ o register area (all other bits are used to control other block func- tions). the run mode (?0? is entered by reseting. these halt states can be released by requesting an interrupt or resetting. table 3.4 (2) shows how to release the halt state. if the cpu is in the ei state for non-maskable or maskable interrupt, the interrupt will be acknowledged by the cpu and the cpu starts interrupt processing. if the cpu is in the di state fro maskable interrupt, the cpu starts the execu- tion from the instruction following halt instruction, but the interrupt request ?g remains at ?? even when halt state is released by reset operation, the state (including the built-in ram) just before entering the halt can be retained. however, if halt instruction has already been executed in the built-in ram, the ram contents may not be retained. figure 3.4 (1). halt mode setting register
30 toshiba corporation TMP90CM36 3.4.1 run mode figure 3.4 (2) shows the timing for releasing the halt state by an interrupt during run mode. in the run mode, the system clock inside mcu does not stop even after halt instruction has been executed; the cpu merely stops executing instruc- tions. accordingly, the cpu repeats dummy cycle until halt state, interrupt r equests are sampled at the fall edge of clk signal. figure 3.4 (2). halt release timing using interrupts in run mode
toshiba corporation 31 TMP90CM36 3.4.2 idle1 mode figure 3.4 (3) shows the timing used for releasing the halt mode by interrupts in the idle1 mode. in the idle1 mode, only the internal oscillator operates, the system clock inside mcu stops and clk signal is ?ed to ?? in the halt state, interrupt requests are sampled asyn- chronously with the system clock but sampling is performed synchronously with the system clock, whereas the halt release (restart of operation) is performed synchronously with it. figure 3.4 (3). halt release timing using interrupts in the idle1 mode
32 toshiba corporation TMP90CM36 3.4.3 stop mode figure 3.4 (4) shows the timing of halt release caused by interrupts in stop mode. in the stop mode, all interval circuits stop, including internal oscillator. when the stop mode is activated, all pins except special ones are put in the high-impedance state, iso- lated from the internal operation of mcu. table 3.4 (1) shows the state of each pin in the stop mode. however, if wdmod (drive enable: bit 0 of memory address ffech) of th built-in i/o register is set to ?? the pre-halt state of the pins can be retained. the register is cleared to ??by reset operation. when the cpu accepts an interrupt request, the internal oscillator ?st restarts. however, to get the stabilized oscilla- tion, the system clock starts its output after the time set by warming up counter has passed. wdmod (warm- ing up: bit 4 at memory address ffech) is used to set up the warming up time. warming up is executed for 2 14 clock oscil- lation time when this bit is set to ?? while 2 16 clock oscillation time when set to ?? this bit is cleared to ??by reset opera- tion. figure 3.4 (4). halt release timing using interrupts in stop mode
toshiba corporation 33 TMP90CM36 the internal oscillator can also be restarted by inputting the reset signal ??to the cpu. however, the warming up counter remains inactive in order to make the cpu rapidly operate when the power is turned on. accordingly, wrong operation may occur due to unstable clocks immediately after the internal oscillator has restarted. to release the halt state by resetting in the stop mode, reset signal must be kept at ??for a suf?ient period of time.
34 toshiba corporation TMP90CM36 : indicates that input mode/input pin cannot be used for input and that the output mode/ output pin have been set to high impedance. input: input is enabled. input: the input gate is operating. fix the input voltage at either ??or ??to prevent the pin ?ating. output: output status. table 3.4 (1) state of pins in stop mode i/o drve = 0 drve = 1 p00 ~ p07 input mode output mode input output p10 ~ p17 input mode output mode input output p20 ~ p27 input mode output mode input output p30 ~ p31 input mode output mode input output p32 ~ p33 input mode output mode input output p40 ~ p47 input mode output mode input output p56 ~ p57 input mode output mode input output p60 ~ p67 input mode p70 ~ p77 input mode output mode output input output nmi daout0 daout1 nmi clk x1 x2 ea input mode output mode output mode input mode output mode input mode output mode input mode input 0v 0v input ? input input 0v 0v input ? input p80 (wdtout ) p81 (int0) p82 (stby ) p83 (ale) output mode input mode input mode output mode input input output input input output
toshiba corporation 35 TMP90CM36 table 3.4 (2) i/o operation release in halt mode
36 toshiba corporation TMP90CM36 3.5 function of ports the TMP90CM36 contains total of 64 i/o port pins. these port pins function not only as the general-purpose i/o ports but also as the i/o ports for the internal cpu and built-in i/o. table 3.5 shows the functions of these port pins. table 3.5 functions of ports these port pins function as the general-purpose i/o port pins by r esetting. the port pins, for which input or output is pro- grammably selectable, function as input ports by resetting. a separate program is required to use them for an internal func- tion.
toshiba corporation 37 TMP90CM36 3.5.1 port 0 (p00 ~ p07) port 0 is the 8-bit general-purpose i/o port p0, each bit of which can be set independently for input or output. the con- trol register p0cr is used to set input or output. reset opera- tions clear all output latch and control register bits to ??and set port 0 to the input mode. in addition to the general-purpose i/o port function, port 0 also functions as an address/data bus (ad0 ~ ad7). when the external memory is accessed, port 0 automatically functions as the address/data bus. figure 3.5 (1). port 0 (p00 ~ p07)
38 toshiba corporation TMP90CM36 figure 3.5 (2). registers for port 0
toshiba corporation 39 TMP90CM36 3.5.2 port 1 (p10 ~ p17) port 1 is the 8-bit general-purpose i/o port p1, each bit of which can be set to input or output. the port 1 control register p1cr is used to set input or output. reset operations clear all output latch and the control register bits to ??and sets all port 1 bits to the input mode. in addition to the general-purpose i/o port function, port 1 also functions as an address bus (a8 ~ a15). this is speci?d by setting the external extended speci?ation register irfl to ??and setting p1cr to the output mode. when the p1cr cleared to ?? port 1 is set to the input mode, regardless of the external extended speci?ation register value. figure 3.5 (3). port 1 (p10 ~ p17)
40 toshiba corporation TMP90CM36 figure 3.5 (4). registers for port 1
toshiba corporation 41 TMP90CM36 3.5.3 port 2 (p20 ~ p27) port 2 is the 8-bit general-purpose i/o port p2, each bit of which can be set to input or output. the port 2 control register p2cr is used to set input or output. reset operations clear all output latch and the control register bits to ??and set port 2 to the input mode. in addition to the general-purpose i/o port function, port 2 also has a timing pulse generator (tpg) output (tpg00 ~ 07, tpg14 ~ tpg17). to use tpg as the output port function, port should be set to output mode, and and port output latch set to ?? (after reset ?? p24 ~ p27 is also used as tpg04 and tpg17 (p24), tpg05 and tpg16 (p25), tpg06 and tpg15 (p26), tpg07 and tpg14 (p27), it selects by the port 2 function register p2fr . p27 is tpg07 output by setting p2 fr ?? tpg07 is = ??by resetting, and the port turns to output mode. figure 3.5 (5). port 2 (p20 ~ p27) figure 3.5 (6) port 2 (p24, p25, p26, p27)
42 toshiba corporation TMP90CM36 figure 3.5 (7). registers for port 2
toshiba corporation 43 TMP90CM36 3.5.4 port 3 (p30 ~ p33) p32, p33 are a 4-bit general-purpose i/o port. the control register p38cr is used for input or output. p30, p31 are output ports. all bits of the output latch are set to ??by resetting, and ??is generated to the output port. access of external memory makes p30, p31 function as the memory control pins (rd and wr ), when set irf2 to ?? when access of an internal memory makes them function, ??is generated always. also function register p38cr is intended for a pseudostatic ram. when set irf2 to ?? and set p38cr to ?? it always functions as rd pin. there- fore, the rd pin outputs ??(enable) when it is an internal memory read and internal i/o read cycle. figure 3.5 (8). port 3 (p30, 31)
44 toshiba corporation TMP90CM36 figure 3.5 (9). port 3
toshiba corporation 45 TMP90CM36 figure 3.5 (10). register for port 3
46 toshiba corporation TMP90CM36 3.5.5 port 4 (p40 - p47) port 4 is the 8-bit general-purpose i/o port, each bit of which can be set for input or output. the control register p4cr is used to set input or output. all bits of the function register are cleared to ??by reset- ting, and the port turns of general-purpose i/o port mode. in addition to the general-purpose i/o port function, p40 ~ 43 have an input/output function for the timing pulse gen- erators output (tpg10 ~ tpg13) function, and p44 ~ p47 have the capture input (cap0 ~ cap3) function. figure 3.5 (11). port 4 (p40, p41, p42, p43)
toshiba corporation 47 TMP90CM36 figure 3.5 (12). port 4 (p44, p45, p46, p47)
48 toshiba corporation TMP90CM36 figure 3.5 (13). register for port 4
toshiba corporation 49 TMP90CM36 3.5.6 port 5 (p50 - p57) port 4 is the 8-bit general-purpose i/o port, each bit of which can be set for input or output. the control register p5cr is used to set input or output. by reset operation, the output latch and the control regis- ter is reset to ?? and port 5 is placed in the input mode. in addition to the general-purpose i/o port function, these ports function as interrupt request input, clock input for timer or event counter, or timer output, or wait input, or clock input for time base counter. (1) p55, p57, p51, p52 when speci?d by port 5 function register p5fr , these ports become the timer out- put. figure 3.5 (14). port 5 (p55, p57, p51, p52)
50 toshiba corporation TMP90CM36 (2) p56 p56 is also used as clock input (ti0) for 8-bit timer 0 external interrupt request input (int3). figure 3.5 (15). port 5 (p56)
toshiba corporation 51 TMP90CM36 (3) p53, p54 these ports are also used as the clock input for 16-bit timer or event counter as well as external interrupt request input. figure 3.5 (16). port 5 (p53, p54)
52 toshiba corporation TMP90CM36 (4) p50 p50 is also used as input external input (exin) for clock input for time base counter. it selects by setting the port 5 function register p5fr . figure 3.5 (17). port (p50)
toshiba corporation 53 TMP90CM36 figure 3.5 (18). registers for port 5
54 toshiba corporation TMP90CM36 3.5.7 port 6 (p60 - p67) port 6 is an 8-bit general-purpose input port with ?ed input function. in addition to its general-purpose input port function, these ports function as analog input pins (an0 ~ an7). figure 3.5 (19). port 6 (p60 ~ p67) figure 3.5 (20). registers for port 6
toshiba corporation 55 TMP90CM36 3.5.8 port 7 (p70 - p77) port 3 is the 8-bit general-purpose i/o port, each bit of which can be set for input or output. the control register p3cr is used to set input or output. by reset operations, all bits of the output latch are set to ?? while all bits of control register are to ?? and port 7 is placed in the input mode. in addition to the general-purpose i/o port function, port 7 function have an internal serial interface input/output function. this is speci?d by function register p23fr. all bits of the function register are cleared to ??by resetting, and the port turns to general-pur- pose i/o mode. figure 3.5 (21). port 7
56 toshiba corporation TMP90CM36 figure 3.5 (22). registers for port 7
toshiba corporation 57 TMP90CM36 figure 3.5 (23). registers for port 7
58 toshiba corporation TMP90CM36 3.5.9 port 8 (p80 - p83) port 8 is the 4-bit general-purpose i/o port, p81, p82 are input-only ports. p80, p83 are output-only ports. in addition to its general-purpose input port function, or watch dog timer out output, these port function as external interrupt request input, or hardware input, or ale output. (1) p81/int0 p81 is the general-purpose input port, is also use as external interrupt request input (int0). int0 is to be used as ??level detection interrupt or rise edge detection interrupt by control register inte2 . figure 3.5 (24). port 8 (p81)
toshiba corporation 59 TMP90CM36 (2) p80 p80 is used both as a general-purpose output port and for wdtout output. bit 1 of the watchdog timer mode register (wdmod: memory address ffddh) and bit 1 of the p38 control register (p38cr: memory address ffa7h) is used to set p80 for wdtout out- put. figure 3.5 (25). port 8 (p80)
60 toshiba corporation TMP90CM36 (3) p82/stby p82 is a general purpose input port, and this port can be used also as hardware standby. by reset opera- tions, the control register p38cr is ?? and p82 is placed in the general-purpose input port. when the control register p38cr is ?? and p82 is placed in the hardware standby input pin. figure 3.5 (26). port 8 (p82)
toshiba corporation 61 TMP90CM36 (4) p83 p83 is output port, and is also used as ale pin. when p83 was 1 chip mode (ea = 1), by reset operations, the control register p38cr is ?? and p83 is placed in the output port. when ale pin uses, and is set to ?? when multi chip mode was is always ?? and p83 become the ale out- put. figure 3.5 (27). port 8 (p83)
62 toshiba corporation TMP90CM36 figure 3.5 (28). registers for port 8
toshiba corporation 63 TMP90CM36 3.6 timers the TMP90CM36 contains four 8-bit timers (timers 0, 1, 2 and 3), each of which can be operated independently. the cas- cade connection allows these timers to be used as 16-bit tim- ers. the following four operating modes are provided for the 8- bit timers. 8-bit interval timer mode (4 timers) 16-bit interval timer mode (2 timers) 8-bit programmable square wave pulse generation (ppg: variable duty with variable cycle) output mode (2 timers) 8-bit pulse width modulation (pwm: variable duty with con- stant cycle) output mode (2 timers) the upper two can be combined (two 8-bit timers and one 16-bit timer). figure 3.6 (1) shows the block diagram of 8-bit timer (timer 0 and timer 1). 8-bit timer (timer 2, 3) are connected to the external clock pin ti2 in the timer 2 up counter input clock. other timer 2 and timer 3 have the same circuit con?ura- tion as timer 0 and timer 1. each interval consists of an 8-bit up-counter, 8-bit comparator, and 8-bit timer register. besides, one timer ?p?p (tff1 or tff3) is provided for each pair of timer 0 and timer 1 as well as timer 2 and timer 3. among the input clock sources for the interval timers, the internal clocks of ?1, ?4, ?16, and ?256 are obtained from the 9-bit prescaler shown in figure 3.6 (2). the operation modes and timer ?p?ps of the 8-bit timer are controlled by ?e control registers t01mod, t23mod, tffcr, trun, and trdc.
64 toshiba corporation TMP90CM36 figure 3.6 (1). block diagram of 8-bit timers (timers 0 and 1)
toshiba corporation 65 TMP90CM36 prescaler this 9-bit prescaler generates the clock input to the 8-bit timers, 16-bit timer/event counters, and baud rate genera- tors by further dividing the fundamental clock (fc) after it has been divided by 4 (fc/4). among them, 8-bit timer uses 4 types of clock: ?1, ?16, and ?256. this prescaler can be run or stopped by the timer opera- tion control register trun . counting starts when is set to ?? while the prescaler is cleared to zero and stops operation when is set to ?? resetting clears to ?? which clears and stops the prescaler . figure 3.6 (2). prescaler
66 toshiba corporation TMP90CM36 up-counter this is an 8-bit binary counter that counts up the input clock pulse speci?d by the timer 0/timer 1 mode reg- ister t01mod and timer 2/timer 3 mode register t23mod. the input clock pulse for timer 0 is selected from ?1 (8/fc), ?4 (32/fc) and ?16 (128/fc). timer 2 input clock is selected from external clock (ti2 pin = p55/ int3) and same the timer 0 in three kinds internal clock. according to the set value of t01mod and t23mod. the input clock of timer 1 and timer 3 differs depend- ing on the operating mode. when set to 16-bit timer mode, the over?w output of timer 0 and timer 2 is used as the input clock. when set to any other mode than 16-bit timer mode, the input clock is selected from the internal clocks ?1 (8/fc), ?16 (128/fc), and ?256 (2048/fc) as well as the comparator output (match detection signal) of timer 0 and timer 2, according to the set value of t01mod and t23mod. example: when tmod = 01, the over?w output of timer 0 becomes the input clock of timer 1 (16-bit timer). when tmod = 00 and t01mod = 01, ?1 (8/fc) becomes the input of timer 1. operation mode is also set by t01mod and t23mod. when reset, it is initialized to t01mod = 00 and t23mod = 00, whereby the up-counter is placed in the 8-bit timer mode. the counting, halt, and clear of up-counter can be controlled for each interval timer by the timer operation control register trun. when reset, all up-counters will be cleared to stop the timers. a timer registers this is an 8-bit register for setting an interval time. when the set value of timer register treg0, treg1, treg2, and treg3 matches the value of up-counter, the comparator match detect signal becomes active. if the set value is 00h, this signal becomes active when the up-counter over?ws. timer registers treg0 and treg2 are of double buffer structure, each of which makes a pair with reg- ister buffer. the treg0 and treg2 control whether the double buffer should be enabled or disabled through the timer register double buffer control register trdc . it is disabled when / = 0, and enabled when they are set to 1. the timing to transfer data from the register buffer to the timer register in the double buffer enable state is the moment 2 n - 1 over?w occurs in pwm mode or the moment compare cycles will be equal in ppg mode. when reset, it will be initialized to = 0 to disable the double buffer. to use the double buffer, write data in the timer register, set and to 1, and write the following data in the register buffer.
toshiba corporation 67 TMP90CM36 figure 3.6 (3). con?uation of timer registers 0 and 2 note: timer register and the register buffer are allo- cated to the same memory address. when / = 0, the same value writ- ten in the register buffer as well as the timer register, while when / = 1 only the register buffer is written. the memory address of each timer register is as fol- lows. treg0: ffc6h treg1: ffc7h treg2: ffc8h treg3: ffc9h all the registers are write-only and cannot be read.
68 toshiba corporation TMP90CM36 figure 3.6 (4). timer 0/timer 1 mode register (t01mod)
toshiba corporation 69 TMP90CM36 figure 3.6 (5). timer 2/timer 3 mode register (t23mod)
70 toshiba corporation TMP90CM36 figure 3.6 (6). 8-bit timer flip?p control register (tffcr)
toshiba corporation 71 TMP90CM36 figure 3.6 (7). timer operation control register (trun)
72 toshiba corporation TMP90CM36 figure 3.6 (8). timer register double buffer control register (trdc)
toshiba corporation 73 TMP90CM36 ? comparators a comparator compares the value in the up-counter with the values to which the timer register is set. when they match, the up-counter is cleared to zero and an interrupt signal (intt0 ~ intt3) is generated. if the timer ?p?p inversion is enabled, the timer ?p?p is inverted at the same time. ? timer flipflop (timer f/f) the status of the timer ?p?p is inverted by the match detect signal (comparator output) of each interval timer and the value can be output to the timer output pins to1 (also used as p55) and to3 (also used as p57). a timer f/f is provided for each pair of timer 0 and timer 1 as well as that of timer 2 and timer 3 and is called tff1 and tff3. tff1 is output to to1 pin, while tff3 is output to to3 pin. the operation of 8-bit timers will be described below: (1) 8-bit timer mode four interval timers 0, 1, 2, and 3 can be used inde- pendently as an 8-bit interval timers. all interval timers operate in the same manner, thus only the operation of timer 1 will be explained below. generating interrupts in a fixed cycle to generate timer 1 interrupt at constant intervals using using timer 1 (intt1), ?st stop timer 1 then set the operation mode, input clock, and synchronization to t01mod and treg1, respectively. then, enable interrupt intt1 and start the counting of timer 1. example: to generate timer 1 interrupt every 40 microseconds at fc = 16mhz, set each reg- ister in the following manner. use the following table for selecting the input clock: table 3.6 (1) 8-bit timer interrupt cycle and input clock interrupt cycle (at fc = 16mhz) resolution input clock 0.5 m s ~ 128ms 0.5 m s ?1 (8/fc) 2 m s ~ 512ms 2 m s ?16 (32/fc) 8 m s ~ 2,048ms 8 m s ?256 (128/fc) 128 m s ~ 32,768ms 128 m s ?256 (2048/fc)
74 toshiba corporation TMP90CM36 generating pulse a 50% square wave pulse the timer ?p?p is inverted at constant intervals, and its status is output to timer output pin (to1). example: to output a 3.0 m s square wave pulse from to1 pin at fc = 16mhz, set each register in the following procedures. either timer 0 or timer 1 may be used, but this example uses timer 1.
toshiba corporation 75 TMP90CM36 figure 3.6 (9). square wave (50% duty) output timing chart a making timer 1 count up by match signal from timer 0 comparator set the 8-bit timer mode and set the comparator output of timer 0 as the input clock to timer 1. figure 3.6 (10)
76 toshiba corporation TMP90CM36 ? output inversion with software the value of timer ?p?p (timer f/f) can be inverted, independent of the timer operation. writing ?0?to tffcr inverts the value of tff1, and writing ?0?into tffcr inverts tff3. ? initial setting of timer flipflop (timer f/f) the value of timer f/f can be initialized to ??or ?? independent of timer operation. for example, write ?0?in tffcr to clear tff1 to ?? while write ?1?in tffcr to set tff1 to ?? note: the value of timer f/f and timer register cannot be read. (2) 16-bit timer mode a 16-bit interval timer is con?ured by using the pair of timer 0 and timer 1 or that of timer 2 and timer 3. as the above two pairs operate in the same manner, only the case of combining timer 0/timer 1 is dis- cussed. to make a a 16-bit interval timer by cascade connect- ing timer 0 and timer 1, set timer 0/timer 1 mode regis- ter t01mod to ?,1? when set in 16-bit timer mode, the over?w output of timer 0 will become the input clock of timer 1, regard- less of the set value of t01mod . table 3.6 (2) shows the relation between the cycle of timer (interrupt) and the selection of input clock. table 3.6 (2) 16-bit timer (interrupt) cycle and input clock interrupt cycle (at fc = 16mhz) resolution input clock 0.5 m s ~ 32.768ms 0.5 m s ?1 (8/fc) 2 m s ~ 131.072ms 2 m s ?16 (32/fc) 8 m s ~ 524.288ms 8 m s ?256 (128/fc) the lower 8 bits of the timer (interrupt) cycle are set by the timer register treg0, and the upper 8 bits are set by treg1. note that treg0 always must be set ?st. (writing data into treg0 disables the comparator temporarily, and the comparator is restarted by writing data into treg1.) setting example: to generate interrupt intt1 every 0.5 seconds at fc = 16mhz, set the following values for timer registers treg0 and treg1. when counting by using ?16 (8 m s @16mhz), 0.5sec ? 8 m s = 62500 = f424h therefore, set treg1 = f4h and treg0 = 24h, respectively. the comparator match signal is output from timer 0 each time the up-counter matches uc0, where the up-counter uc0 is not cleared. with the timer 1 comparator, the match detect signal is output at each comparator timing when up-counter uc1 and treg1 values match. when the match detect signal is output simultaneously from both comparators of timer 0 and timer 1, the up-counters uc0 and uc1 are cleared to ?? and the interrupt intt1 is generated. if inversion is enabled, the value of the timer ?p?p tff1 is inverted.
toshiba corporation 77 TMP90CM36 example: when treg1 = 04h and treg0 = 80h figure 3.6 (11) (3) 8-bit ppg (programmable pulse generation) mode square wave pulse can be generated at any frequency and duty by timer 0 or timer 2. the output pulse may be either low-active or high-active. in this mode, timer 1 and timer 3 cannot be used. timer 0 outputs pulse to to1 pin, (also used as p55), and timer 2 outputs to to3 pin (also used as p57). as an example, the case of timer 0 will be explained below. (timer 2 also functions in the same way).
78 toshiba corporation TMP90CM36 in this mode, a programmable square wave is gener- ated by inverting timer output each time the 8-bit up- counter (uc0) matches the timer registers treg0 and treg1. however, it is required that the set value of treg0 is smaller than that of treg1. though the up-counter (uc1) of timer 1 cannot be used in this mode, timer 1 can be used for counting by setting trun to ?? figure 3.6 (12) shows the block diagram for this mode. figure 3.6 (12). block diagram of 8-bit ppg mode when the double buffer of treg0 is enabled in this mode, the value of register buffer will be shifted in treg0 each time treg1 matches uc0. use of the double buffer makes easy the handling of low duty waves (when duty is varied).
toshiba corporation 79 TMP90CM36 example: generating 1/4 duty 50khz pulse (@fc = 16mhz) calculate the value to be set for timer register to obtain the frequency 50khz, the pulse cycle t should be: 1/50khz = 20 m s. given ?1 = 0.5 m s (@ 16mhz) 20 m s ? 0.5 m s = 40 consequently, to set the timer register 1 (treg1) to treg1 = 40 = 28h and the duty to 1/4, t x 1/4 = 20 m s x 1/4 5 m s 5 m s ? 0.5 m s = 10 therefore, set timer register 0 (treg0) to treg0 = 10 = 0ah.
80 toshiba corporation TMP90CM36 (4) 8-bit pwm (pulse width modulation) mode this mode is valid only for timer 0 and timer 2. in this mode, maximum two pwms of 8-bit resolution (pwm0 and pwm2) can be output. pwm pulse is output to to1 pin (also used as p55) when using timer 0, and to to3 pin (also used as p57) when using timer 2. timer 1 and timer 3 can also be used as 8-bit timer. as an example, the case of timer 0 will be explained below. (timer 2 also operates in the same way.) timer output is inverted when up-counter (uc0) matches the set value of timer register treg0 or when 2n - (n = 6, 7, or 8; speci?d by t01mod ) counter over?w occurs. up-counter uc0 is cleared when 2n - 1 counter over?w occurs. for example, when n = 6, 6-bit pwm will be output, while when n = 7, 7-bit pwm will be output. to use this pwm mode, the following conditions must be satis?d. (set value of timer register) < (set value of 2 n - 1 counter over?w) (set value of timer register) 1 0 figure 3.6 (13) shows the block diagram of this mode. figure 3.6 (11). block diagram of 8-bit pwm mode
toshiba corporation 81 TMP90CM36 in this mode, the value of register buffer will be shifted in treg0 2 n - 1 over?w is detected when the double buffer of treg0 is enabled. use of the double buffer makes easy the handling of small duty waves. example: to output the following pwm waves to to1 pin using timer 0 at fc = 16mhz. calculate the value to be set for timer register to realize 63.5 m s of pwm cycle by ?1 = 0.5 m s (@ = 16mhz), 63.5 m s ? 0.5 m s = 127 = 2 7 - 1 consequently, n should be set to 7. as the period of low level is 36 m s, for ?1 = 0.5 m s, set the following value for treg0. 36 m s ? 0.5 m s = 72 = 48h
82 toshiba corporation TMP90CM36 (5) table 3.6 (4) shows the list of 8-bit timer modes . (note) ? dont care lower timer external input clock has t2clk. but it does not have t0clk. table 3.6 (3) pwm cycle and the setting of 2 n - 1 counter formula pwm cycle (@ fc = 16mhz) ?1 (8/fc) ?4 (32/fc) ?16 (128/fc) 2 6 - 1 (2 6 - 1) x ?n 31.5 m s 126 m s 504 m s 2 7 - 1 (2 7 - 1) x ?n 63.5 m s 254 m s 1.01ms 2 8 - 1 (2 8 - 1) x ?n 127 m s 510 m s 2.04ms table 3.6 (4) timer mode setting registers register name t01mod (t23mod) tffcr name of bit in register t01m (t32m) pwm1 (pwm3) t1clk (t3clk) t0clk (t2clk) ff1is (ff3is) function timer mode pwm cycle upper timer input clock lower timer input clock timer f/f invert signal select 16-bit timer mode 01 external clock ?1, ?16, ?256 (01, 10, 11) 8-bit timer x 2 channels 00 lower timer match ?1, ?16, ?256 (01, 01, 10, 11) external clock ?1, ?16, ?256 (01, 01, 10, 11) 0: lower timer output 1: upper timer output 8-bit ppg x 1 channel 10 external clock ?1, ?16, ?256 (01, 01, 10, 11) 8-bit pwm x 1 channel 11 2 6 - 1, 2 7 - 1, 2 8 - 1 (01, 10, 11) external clock ?1, ?16, ?256 (01, 01, 10, 11) 8-bit timer x 1 channel 11 ?1, ?14, ?16 (01, 10, 11) output disabled
toshiba corporation 83 TMP90CM36 3.7 multi-function 16-bit timer/event counter (timer 4) the TMP90CM36 has one multifunctional 16-bit timer/event counter with the following operation modes: 16-bit timer 16-bit event counter 16-bit programmable pulse generation (ppg) frequency measurement pulse width measurement time differential measurement figure 3.7 (1) shows the block diagram of 16-bit timer/ event counter.
84 toshiba corporation TMP90CM36 figure 3.7 (1). block diagram of 16-bit timer/event counter (timer 4)
toshiba corporation 85 TMP90CM36 timer/event counter con sists of 16-bit up-counter, two 16- bit timer registers, and two 16-bit capture registers, two com- parators, register buffer, capture input controller, timer ?p?p, and the control circuit. timer/event counter is controlled by 4 control registers: t4mod, t4ffcr, trun, and trdc. trun register includes 8-bit timer controller. for trun and trdc registers, see fig- ure 3.6 (7) and figure 3.6 (8). figure 3.7 (2). 16-bit timer/event counter (timer 4) control/mode register (1/2)
86 toshiba corporation TMP90CM36 figure 3.7 (2). 16-bit timer/event counter (timer 4) control/mode register (2/2)
toshiba corporation 87 TMP90CM36 figure 3.7 (3). 16-bit timer/event counter timer ?p?p control register
88 toshiba corporation TMP90CM36 up-counter (uc16) uc16 is a 16-bit binary counter which counts up according to the input clock speci?d by t4mod register. as the input clock, one of the internal clocks ?1 (8/ fc), ?4 (32/fc), and ?i6 (128/fc) from 9-bit prescaler (also used as 8-bit timer), and external clock from ti4 pin (commonly used as p46/int1 pin) can be selected. when reset, it will be initialized to = 00 to select ti4 input mode. counting, stop, or clearing of the counter in controlled by timer operation control register trun . when clearing is enabled, up-counter uc16 will be cleared to zero each time it coincides matches the timer register treg5. the ?lear enable/disable?is set by t4mod . if clearing is disabled, the counter operates as a free- running counter. timer registers (treg4 and treg5) these two 16-bit registers are used to set the value of the counter. when the value of up-counter uc16 matches the set value of this timer register, the com- parator match detect signal will become active. setting data for timer register (treg4 and treg5) is executed using 16-bit transfer instruction od using 8- bit transfer instruction twice for lower 8 bits and upper 8 bits in order. treg4 timer register is of double buffer structure, which is paired with register buffer. treg4 controls whether the double buffer should be enabled or dis- abled, using the timer register double buffer control register trdc ; disable when = 0, while enable when = 1. when the double buffer is enabled, the timing to trans- fer data from the register buffer to the timer register is at the match between the up-counter and treg5. when reset, it will be initialized to = 0, whereby the double buffer is disabled. to use the dou- ble buffer, write data in the register buffer. treg4 and register buffer 4 are allocated to the same memory addresses ffcfh and ffd0h. when = 1, the value is written into only the register buffer. a capture register (cap1 and cap2) these 16-bit registers are used to hold the values of the up-counter uc16. data in the capture registers should be read by a 2- byte data load instruction or two 1-byte data load instruction, from the lower 8 bits followed by the upper 8 bits.
toshiba corporation 89 TMP90CM36 ? capture input control circuit this circuit controls the timing to latch the value of up- counter uc16 into cap1 and cap2. the latch timing of capture register is controlled by register t4mod . ?when t4mod = 00 capture function is disabled. disable is the default on reset. ?when t4mod = 01 data is loaded to cap1 at the rise edge of ti4 pin (commonly used as p53/int1) input, while data is loaded to cap2 at the rise edge of ti5 pin (commonly used as p57/int2) input. (time difference measure- ment) ?when t4mod = 10 data is loaded to cap1 at the rise edge of ti4 pin input, while to cap2 at the fall edge. only in this set- ting, interrupt int1 occurs at fall edge. (pulse width measurement) ?when t4mod = 11 data is loaded to cap1 at the rise edge of timer ?p?p tff1, while to cap2 at the fall edge. (frequency mea- surement) besides, the value of up-counter can be loaded to capture registers by software. whenever ??is written in t4mod , the current value of up-counter will be loaded to capture register cap1. it is necessary to keep the prescaler in run mode (trun to be ??. ? comparators (cp4, cp5) these are 16-bit comparators which compare the up- counter uc16 value with the set value of treg4 or treg5 to detect the match. when a match is detected, the comparators generate an interrupt intt4 and intt5, respectively. the up-counter uc16 is cleared only when uc16 matches treg5. (the clearing of up-counter uc16 can be disabled by set- ting t4mod = 0.) ? timer flipflop (tff4) this ?p?p is inverted by the match detect signal from the comparators (cp4 and cp5) and the latch signals to the capture registers (cap1 and cap2). disable/ enable of inversion can be set for each element by t4ffcr . tff4 will be inverted when ?0?is written in t4ffcr . also, it is set to ??when ?0?is written, and cleared to ??when ?0?is written. the value of tff4 can be output to the timer output pin to4 (com- monly used as p51). ? timer flipflop (tff5) this ?p?p is inverted by the match detect signal from the comparator cp5 and the latch signal to the cap- ture register cap2. tff5 will be inverted when ?0?is written in t4ffcr . also, it is set to ?? when ?0?is written, and cleared to ??when ?0?is written. the value of tff5 can be output to the timer output pin to5 (commonly used as p52). (1) 16-bit timer mode in this example, the interval time is set in the timer reg- ister treg5 to generate the interrupt intt5.
90 toshiba corporation TMP90CM36 (2) 16-bit event counter mode in timer mode as described in above (1), the timer can be used as an event counter by selecting the external clock (ti4 pin input) as the input clock. to read the value of the counter, ?st perform ?oftware capture?once and read the captured value. the counter counts at the rising edge of ti4 pin input. ti4 pin can also be used as p46/int1. (3) 16-bit programmable pulse generation (ppg) mode the ppg mode is entered by inversion of the timer ?p- ?p tff4 that is to be enabled bu the match of the up- counter uc16 with the timer register treg4 or 5 and to be output to to4 (also used as p51). in this mode, the following conditions must be satis?d.
toshiba corporation 91 TMP90CM36 when the double buffer of treg4 is enabled in this mode, the value of register buffer 4 will be shifted in treg4 at match with treg5. this feature makes easy the handling of low duty waves (when duty rate is var- ied). (4) application examples of capture function the loading of up-counter (uc16) vaules into the cap- ture registers cap1 and cap2, the timer ?p?p tff4 inversion due to the match detection by comparators cp4 and cp5, and the output of the tff4 status to to4 pin can be enabled or disabled. combined with interrupt function, they can be applied in many ways, for example. one-shot pulse output by using external trigger pulse frequency measurement a pulse width measurement ? time difference measurement one-shot pulse output from the rising edge of exter- nal trigger pulse. set the up-counter uc16 in free-running mode with the internal input clock, input the external trigger pulse from ti4 pin, and load the value of up-counter into cap- ture register cap1 at the rise edge of the ti4 pin. then set to t4mod = 01. when the interrupt int1 is generated at the rise edge of ti4 pin, set the cap1 value (c) plus a delay time (d) to treg4 (= c + d), and set the above set value (c + d) plus a one-shot pulse width (p) to treg5 (= c + + d + p). when the interrupt int1 occurs the t4ffcr regis- ter should be set that the tff4 inversion is enabled only when the up-counter value matches treg4 or 5. when interrupt intt5 occurs, this inversion will be dis- abled. figure 3.7 (4). one-shot pulse output (with delay)
92 toshiba corporation TMP90CM36
toshiba corporation 93 TMP90CM36 when delay time is unnecessary, invert timer ?p?p tff4 when the up-counter value is loaded into loaded into capture register 1 (cap1), and set the cap1 value (c) plus the one-shot pulse width (p) to treg5 when the interrupt int1 occurs. the tff4 inversion should be enabled when the up-counter (uc16) value matches treg5, and disabled when generating the interrupt intt5. figure 3.7 (5). one-shot pulse output (without delay) frequency measurement the frequency of the external clock can be measured in this mode. the clock is input through the ti4 pin, and its frequency is measured by the 8-bit timers (timer 0 and timer 1) and the 16-bit timer/event counter (timer 4). the ti4 pin input should be selected for the input clock of timer 4. the value of the up-counter is loaded into the capture register cap1 at the rise edge of the timer ?p?p tff1 of 8-bit timers (timer 0 and timer 1), and cap2 at its fall edge. the frequency is is calculated by the difference between the loaded values in cap1 and cap2 when the interrupt (intt0 or intt1) is generated by either 8- bit timer. figure 3.7 (6). frequency measurement
94 toshiba corporation TMP90CM36 for example, if the value for the level ??width of tff1 of the 8-bit timer is set to 0.5 sec. and the difference between cap1 and cap2 is 100, the frequency will be 100/0.5 [sec.] = 200[hz]. a pulse width measurement this mode allows to measure the ??level width of an external pulse. while keeping the 16-bit timer/event counter counting (free-running) with the internal clock input, the external pulse is input though the ti4. then the capture function is used to load the uc16 values into cap1 and cap2 at the rising edge and falling edge of the external trigger pulse, respectively. the interrupt int1 occurs at the falling edge of ti4. the pulse width is obtained from the difference between the values of cap1 and cap2 and the internal clock cycle. for example, if the internal clock is 0.8 microseconds and the difference between cap1 and cap2 is 100, the pulse width will be 100 x 0.8 = 80 microseconds. figure 3.7 (7). pulse width measurement note: only in this pulse width measuring mode ( t4mod = 10), external interrupt int1 occurs at the falling edge of ti4 pin input. in other modes, it occurs at the rising edge. the width of ??level can be measured from the differ- ence between the ?st c2 and the second c1 at the second int1 interrupt.
toshiba corporation 95 TMP90CM36 ? time difference measurement this mode is used to measure the difference in time between the rising edges of external pulses input through ti4 and ti5. keep the 16-bit timer/event counter (timer 4) counting (free-running) with the internal clock, and load the uc16 value into cap1 at the rising edge of the input pulse to ti4. then the interrupt int1 is generated. similarly, the uc16 value is loaded into cap2 at the rising edge of the input pulse to ti5, generating the interrupt int2. the time difference between these pulses can be obtained from the difference between the time counts at which loading the up-counter value into cap1 and cap2 has been done. figure 3.7 (8). time difference measurement
96 toshiba corporation TMP90CM36 3.8 serial channels the TMP90CM36 contains three serial channels (sio0,1, 2). the three serial channels have the following operation modes. in mode 1 and mode 2, parity bit can be added. mode 3 has a wake-up function for making the master controller start slave controllers in serial link (multi-controller system). figure 3.8 (1) shows the data format (1 frame) for each mode. figure 3.9 (1). data formats
toshiba corporation 97 TMP90CM36 the serial channel has a buffer register for transmitting and receiving operations, in order to temporarily store trans- mitted or received data, so that transmitting and receiving operations can be done independently (full duplex). however, in i/o interface mode, sclk (serial clock) pin is commonly used for both transmission and receiving, the chan- nel becomes half-duplex. the receiving buffer register is of a double buffer structure to prevent the occurrence of overrun error and provides one frame of margin before cpu reads the received data. namely, the one buffer stores the already received data while the other buffer receives the next frame data. in the uart mode, a check function is added not to start the receiving operation by error start bits due to noise. the channel starts receiving data only when the start bit is detected to be normal at least twice in three samplings. when the transmission buffer becomes empty and requests the cpu to send the next transmission data, or when data is stored in the transmission buffer and the cpu is requested to read the data, inttx or intrx interrupt occurs. besides, if an overrun error, parity error, or framing error occors during receiving operation, ?g sccr will be set. in the i/o interface mode, it is possible to input synchro- nous signals as well as to transmit or receive data by an exter- nal clock. the sio0 or sio1 includes a special baud rate generator, which can set any baud rate can be set by dividing by the fre- quency of 4 clocks (?0, ?2, ?8, and ?32) from the internal prescaler (shared by 8-bit/16-bit timer) by the value of 2 to 16. internal clock (sio2) is able to select in speed from ?0, ?1, ?4, and ?16.
98 toshiba corporation TMP90CM36 (1) serial channel (sio0) (3.8.1 ~ 3.8.3) 3.8.1 control registers the serial channel sio0 is controlled by 4 control registers scmod0, sccr0, brgcr0, and p7fr. transmitted and received data are stored in register scbuf0. figure 3.8 (2). serial channel mode register (scmod0)
toshiba corporation 99 TMP90CM36 figure 3.8 (3). serial channel mode register (sccr0) figure 3.8 (4). serial transmission/receiving buffer registers (scbuf0)
100 toshiba corporation TMP90CM36 figure 3.8 (5). baud rate generator control register (brgcr0)
toshiba corporation 101 TMP90CM36 figure 3.8 (6). port 7 function register
102 toshiba corporation TMP90CM36 3.8.2 con?uration figure 3.8 (7) shows the block diagram of the serial channel. figure 3.8 (7). block diagram of the serial channel (sio0)
toshiba corporation 103 TMP90CM36 baud rate generator baud rate generator comprises of a circuit that gener- ates transmission and receiving clocks that determine the transfer rate of the serial channel. the input clock to the baud rate generator, ?0 (fc/4), ?2 (fc/16), ?8 (fc/64), or ?32 (fc/256) is generated by the 9-bit prescaler which is shared by the timers. one of these input clocks is selected by the baud rate genorator control register brgcr0 . the baud rate generator includes a 4-bit frequency divider, which divides frequency by 2 ~ 16 values to determine the transfer rate. how to calculate a transfer rate when the baud rate generator is used is explained below. ?uart mode the relation between the input clock and the source clock (fc) is as follows. ?0 = fc/4 ?2 = fc/16 ?8 = fc/64 ?32 = fc/256 accordingly, when source clock fc is 12.288mhz, input clock ?2 (fc/16), frequency divider is 5, the transfer in uart mode becomes as follows. = 12.288 x 10 6 /16 / 5 / 16 = 9600 (bps) table 3.8 (1) shows an example of the transfer in uart mode. also with 8-bit timer 0, the serial channel (sio0) can get a transfer rate. table 3.8 (2) shows an example of baud rate using timer 0. table 3.8 (1) selection of transfer rate (1) (when baud rate generator is used) unit: kbps source clock (fc) input clock ?0 (fc/4) ?2 (fc/16) ?8 (fc/64) ?32 (fc/256) frequency clock 9.8304mhz 2457.600 614.400 153.600 38.400 2 76.800 19.200 4.800 1.200 4 38.400 9.600 2.400 0.600 8 19.200 4.800 1.200 0.300 0 9.600 2.400 0.600 0.150 12.288mhz 3072.000 786.000 192.000 48.000 5 38.400 9.600 2.400 0.600 a 19.200 4.800 1.200 0.300 14.7456mhz 3686.400 921.600 230.400 57.600 3 76.800 19.200 4.800 1.200 6 38.400 9.600 2.400 0.600 c 19.200 4.800 1.200 0.300
104 toshiba corporation TMP90CM36 table 3.8 (2). selection of transfer rate (2) (when timer 0 (input clock ?1) is used) unit: kbps fc 12.288 mhz 12 mhz 9.8304 mhz 8 mhz 6.144 mhz treg0 1h 96 76.8 62.5 48 2h 48 38.4 31.25 24 3h 32 31.25 16 4h 24 19.2 12 5h 19.2 9.6 8h 12 9.6 6 ah 9.6 4.8 10h 6 4.8 3 14h 4.8 2.4 how to calculate the transfer rate (when timer 0 is used) input clock of timer 0 ?1 = fc/8 ?4 = fc/32 ?16 = fc/128 serial clock generation circuit this circuit generates the basic clcok for transmitting and receiving data. asynchronous communication (uart) mode according to the setting of scmod0 , the above baud rate generator clock, internal clock ? (fc/ 2) (312.5 kbaud at 10mhz), or the match detect signal from timer 0 will be selected to generate the basic clock siock0. a receiving counter the receiving counter is a 4-bit binary counter used in asynchronous communication (uart) mode and counts up by sioclk0 clock. 16 pulses of sioclk0 are used for receiving 1 bit of data, and the data is sampled three times at the 7th, 8th and 9th clock. with the three samples, the received data is evaluated by the rule of majority. for example, if the sampled data is ?? ??and ??at 7th, 8th and 9th clock, respectively, the received data is evaluated as ?? the sampled data ?? ?? and ?? is evaluated that the received data is ?? ? receiving control asynchronous communication (uart) mode the receiving control has a circuit for detecting the start bit by the rule of majority. when two or more ??are detected during 3 samples, it is recognized as normal start bit and the receiving operation is started. data being received are also evaluated by the rule of majority.
toshiba corporation 105 TMP90CM36 ? receiving buffer to prevent overrun from occurring, the receiving buffer has a double structure. received data are stored one bit by one bit in the receiving buffer 1 (shift register type). when 7 bits or 8 bits of data are stored in the receiving buffer 1, the stored data are transferred to another receiving buffer 2 (scbuf0), generating an interrupt intrx0. the cpu reads only receiving buffer 2 (scbuf0). even before the cpu reads the receiving buffer 2 (scbuf0), the received data can be stored in receiving buffer 1 . however, unless the receiving buffer 2 (scbuf0) is read before all bits of the next data are received by the receiving buffer 1, an overrun error occurs. if an overrun error occurs, the contents of receiving buffer 1 will be lost, although the contents of receiving buffer 2 and sccr0 is still preserved. the parity bit added in 8-bit uart mode and the most signi?ant bit (msb) in 9-bit uart mode are stored in sccr0 . when in 9-bit uart, the wake-up function of the slave controllers is enabled by setting scmod0 to ?? and interrupt intrx occurs only when sccr0 is set to ?? ? transmission counter transmission counter is a 4-bit binary counter which is used in asynchronous communication (uart) mode and, like a receiving counter, counts by sioclk0 clock, generating txdclk0 every 16 clock pulses. ? transmission controller asynchronous communication (uart) mode when the transmission data are written in the trans- mission buffer sent from the cpu, transmission starts at the rising edge of the next txdclk0, generating a transmission shift clock txdsft0. 3 transmission buffer transmission buffer scbuf0 shifts out and sends the transmission data written from the cpu from the least signi?ant bit (lsb) in order, using transmission shift clock txdsft0 which is generated by the transmis- sion control. when all bits are shifted out, the transmis- sion buffer becomes empty and generates inttx0 interrupt. parity control circuit when serial channel control register sccr0 is set to ??, it is possible to transmit and receive data with parity. however, parity can be added only in 7-bit uart or 8-bit uart mode. with sccr0 register, even (odd) parity can be selected. for transmission, parity is automatically generated according to the data written in the transmission buffer scbuf, and data are transmitted after being stored in scbuf0 when in 7-bit uart mode while in scmod0 in 8-bit uart mode. and must be set before transmission data are written in the transmission buffer. for receiving, data are shifted in the receiving buffer 1, and parity is added after the data are transferred in the receiving buffer 2 (scbuf0), and then compared with of scbuf0 when in 7-bit uart mode and with sccr0 when in 8-bit uart mode. if they are not equal, a parity error occurs, and sccr0 ?g is set.
106 toshiba corporation TMP90CM36 error flag three error ?gs are provided to increase the reliability of receiving data. 1) overrun error (sccr0 ) if all bits of the next data are received in receiving buffer 1 while valid data are still stored in receiving buffer 2 (scbuf0), an overrun error will occur. 2) parity error (sccr0 ) the parity generated for the data shifted in receiving buffer 2 (scbuf0) is compared with the parity bit received from the rxd0 pin. if they are not equal, a parity error occurs. 3) framing error (sccr0 ) the stop bit of received data is sampled three times around the center. if the majority results is ?? a fram- ing error occurs. 11 generation timing 1) uart mode note: framing error occurs after an interrupt has occurred. therefore, to check for framing error during interrupt operation, it is necessary to wait for 1 bit period of time. receiving mode 9 bit 8 bit + parity 8 bit, 7 bit + parity, 7 bit interrupt timing center of last bit (bit 8) center of last bit (parity bit) center of stop bit framing error timing center of stop bit center of stop bit center of stop bit parity error timing center of last bit (bit 8) center of last bit (parity bit) center of stop bit over-run error timing center of last bit (bit 8) center of last bit (parity bit) center of stop bit transmitting mode 9 bit 8 bit + parity 8 bit, 7 bit + parity, 7 bit interrupt timing just before last bit is transmitted ??
toshiba corporation 107 TMP90CM36 3.8.3 action explanation (1) mode 1 (7-bit uart mode) 7-bit mode can be set by setting serial channel mode reg- ister scmod0 to ?1? in this mode, a parity bit can be added, and the addi- tion of a parity bit can be enabled or disabled by serial channel control register. sccr0 , and even parity or odd parity is selected by sccr0 when is set to ??(enable). setting example: when transmitting data with the fol- lowing format, the control registers should be set as described below.
108 toshiba corporation TMP90CM36 (2) mode 2 (8-bit uart mode) 8-bit uart mode can be set by setting serial channel mode register scmod0 to ?0? in this mode, a parity bit can be added, the addition of a parity bit is enabled or disabled by sccr0 . sccr0 , and even parity or odd parity is selected by sccr0 when is set to ??(enable). setting example: when receiving data with the fol- lowing format, the control registers should be set as described below.
toshiba corporation 109 TMP90CM36 (3) mode 3 (9-bit uart mode) 9-bit uart mode can be speci?d by setting scmod0 to ?1? in this mode, parity bit cannot be added. for transmission, the msb (9th bit) is written in scmod0 , while in receiving it is stored in sccr0 . for writing or reading the buffer, the msb is read or written ?st then scbuf0. w ake-up function in 9-bit uart mode, the wake-up function of slave controllers is enabled by setting scmod0 to ?? the interrupt intrx0 occurs only when sccr0 = 1. figure 3.8 (8). serial link using the wake-up function
110 toshiba corporation TMP90CM36 protocol select the 9-bit uart mode for the master and slave controllers. set the scmod0 bit of each slave control- ler to ??to enable data receiving. a the master controller transmits one-frame including the 8-bit select code for the slave controllers. the msb (bit 8) scmod0 is set to ?? ? each slave controller receives the above frame, and clears wu bit to ??if the above select code matches its own select code. ? the master controller transmits data to the specified slave controller whose scmod0 bit is cleared to ?? the msb (bit 8) scmod0 is set to ?? ? the other slave controllers (with scmod0 bit remaining at ?? ignore the receiving data because their msbs (bit 8 or sccr0 ) are set to ??to disable the interrupt intrx0. when the wu0 bit is cleared to ?? the interrupt intrx0 occurs, so that the slave controller can read the receiving data. the slave controllers (wu0 = 0) transmit data to the master controller, and it is possible to indicate the end of data receiving to the master controller by this transmission. setting example: to link two slave controllers seri- ally with the master controller, and use the internal clock ?1 (fc/2) as the transfer clock .
toshiba corporation 111 TMP90CM36
112 toshiba corporation TMP90CM36 (1) serial channel (sio1) (3.8.4 ~ 3.8.6) 3.8.4 control registers the serial channel sio1 is controlled by 4 control registers scmod1, sccr1, brgcr1, and p7fr. transmitted and received data are stored in register scbuf1 figure 3.8 (9). serial channel mode register (scmod1)
toshiba corporation 113 TMP90CM36 figure 3.8 (10). serial channel mode control register (sccr1) figure 3.8 (11). serial transmission/receiving registers (scbuf1)
114 toshiba corporation TMP90CM36 figure 3.8 (12). baud rate generator control registers (brgcr1)
toshiba corporation 115 TMP90CM36 figure 3.8 (13). port 7 function register
116 toshiba corporation TMP90CM36 3.8.5 con?uration figure 3.8 (14) shows the serial channel block diagram. figure 3.8 (14). serial channel (sio2) block diagram
toshiba corporation 117 TMP90CM36 baud rate generator baud rate generator comprises a circuit that generates transmission and receiving clocks that determine the transfer rate of the serial channel. the input clock to the baud rate generator, ?0 (fc/4), ?2 (fc/16), ?8 (fc/64), or ?32 (fc/256) is generated by the 9-bit prescaler which is shared by the timers. one of these input clocks is selected by the baud rate generator control register brgcr1 . the baud rate generator includes a 4-bit frequency divider, which divides frequency by 2 ~ 16 values to determine the transfer rate. how to calculate a transfer rate when the baud rate generator is used is explained below. ?uart mode ?i/o interface mode the relation between the input clock and the source clock (fc) is as follows. ?0 = fc/4 ?2 = fc/16 ?8 = fc/64 ?32 = fc/256 accordingly, when source clock fc is 12.288mhz, input clock ?2 (fc/16), frequency divider is 5, the transfer in uart mode becomes as follows. = 12.288 x 10 6 /16 / 5 / 16 = 9600 (bps) table 3.8 (1) shows an example of the transfer in uart mode. also with 8-bit timer 1, the serial channel (sio1) can get transfer rate. table 3.8 (2) shows an example of baud rate using timer 2. 2
118 toshiba corporation TMP90CM36 table 3.8 (3) selection of transfer rate (1) (when baud rate generator is used) unit: kbps source clock (fc) input clock ?0 (fc/4) ?2 (fc/16) ?8 (fc/64) ?32 (fc/256) frequency divisor 9.8304mhz 2457.600 614.400 153.600 38.400 2 76.800 19.200 4.800 1.200 4 38.400 9.600 2.400 0.600 8 19.200 4.800 1.200 0.300 0 9.600 2.400 0.600 0.150 12.288mhz 3072.000 786.000 192.000 48.000 5 38.400 9.600 2.400 0.600 a 19.200 4.800 1.200 0.300 14.7456mhz 3686.400 921.600 230.400 57.600 3 76.800 19.200 4.800 1.200 6 38.400 9.600 2.400 0.600 c 19.200 4.800 1.200 0.300
toshiba corporation 119 TMP90CM36 table 3.8 (4) selection of transfer rate (2) (when timer 0 (input clock ?1) is used) unit: kbps fc 12.288 mhz 12 mhz 9.8304 mhz 8 mhz 6.144 mhz treg2 1h 96 76.8 62.5 48 2h 48 38.4 31.25 24 3h 32 31.25 16 4h 24 19.2 12 5h 19.2 9.6 8h 12 9.6 6 ah 9.6 4.8 10h 6 4.8 3 14h 4.8 2.4 how to calculate the transfer rate (when timer 2 is used0) input clock of timer 2 ?1 = fc/8 ?4 = fc/32 ?16 = fc/128 serial clock generation circuit this circuit generates the basic clock for transmitting and receiving data. 1) i/o interface mode when in sclk1 output mode with the setting of sccr1 = ?? the basic clock will be gener- ated by dividing by 2 the output of the baud rate gen- erator described before. when in sclk1 input mode with the setting of sccr1 = ?? the rising edge or the falling edge will be detected according to the setting of sccr1 register to generate the basic clock. 2) asynchronous communication (uart) mode according to the setting of scmod1 , the above baud rate generator clock, internal clock ? (fc/ 2) (312.5 kbaud at 10mhz), or the match detect signal from timer 0 will be selected to generate the basic clock siock. a receiving counter the receiving counter is a 4-bit binary counter used in asynchronous communication (uart) mode and counts up by sioclk1. 16 pulses of sioclk1 are used for receiving 1 bit of data, and the data is sam- pled three times at the 7th, 8th and 9th clock. with the three samples, the received data is evaluated by the rule of majority. for example, if the sampled data is ?? ??and ??at 7th, 8th and 9th clock, respectively, the received data is evaluated as ?? the sampled data ?? ?? and ?? is evaluated that the received data is ??
120 toshiba corporation TMP90CM36 ? receiving control 1) i/o interface mode when in sclk1 output mode with the setting of sccr1 = ?? rxd1 signal will be sampled at the rising edge of shift clock which is output to slck pin. when in sclk1 input mode with the setting of sccr1 = ?? rxd1 signal will be sampled at the ris- ing edge or the falling edge of sclk1 input according to the setting of sccr1 register. 2) asynchronous communication (uart) mode the receiving control has a circuit for detecting the start bit by the rule of majority. when two or more ??are detected during 3 samples, it is recognized as normal start bit and the reciving operation is started. data being received are also evaluated by the rule of majority. ? receiving buffer to prevent overrun from occurring, the receiving buffer has a double structure. received data are stored one bit by one bit in the receiving buffer 1 (shift register type). when 7 bits or 8 bits of data are stored in the receiving buffer 1, the stored data are transferred to another receiving buffer 2 (scbuf1), generating an interrupt intrx1. the cpu reads only receiving buffer 2 (scbuf1). even before the cpu reads the receiving buffer 2 (scbuf1), the received data can be stored in receiving buffer 1 . however, unless the receiving buffer 2 (scbuf1) is read before all bits of the next data are received by the receiving buffer 1, an overrun error occurs. if an overrun error occurs, the contents of receiving buffer 1 will be lost, although the contents of receiving buffer 2 and sccr1 is still pre- served. the parity bit added in 8-bit uart mode and the most signi?ant bit (msb) in 9-bit uart mode are stored in sccr1 . when in 9-bit uart, the wake-up function of the slave controllers is enabled by setting scmod1 to ?? and interrupt intrx occurs only when sccr1 is set to ?? ? transmission counter transmission counter is a 4-bit binary counter which is used in asynchronous communication (uart) mode and, like a receiving counter, counts by sioclk1 clock, generating txdclk1 every 16 clock pulses. ? transmission controller 1) i/o interface mode in sclk1 output mode with the setting of sccr1 = ?? the data in the transmission buffer are output bit by bit to txd1 pin at the rising edge of shift clock which is output from slck1 pin. in sclk1 input mode with the setting of sccr1 = ?? the data in the transmission buffer are output bit by bit to txd1 pin at the rising edge or falling edge of sclk input according to the setting of sccr1 register. 2) asynchronous communication (uart) mode when the transmission data are written in the trans- mission buffer sent from the cpu, transmission starts at the rising edge of the next txdclk1, generating a transmission shift clock txdsft1. 3 transmission buffer transmission buffer scbuf1 shifts out and sends the transmission data written from the cpu from the least signi?ant bit (lsb) in order, using transmission shift clock txdsft1 which is generated by the transmis-
toshiba corporation 121 TMP90CM36 sion control. when all bits are shifted out, the transmis- sion buffer becomes empty and generates inttx1 interrupt. parity control circuit when serial channel control register sccr1 is set to ??, it is possible to transmit and receive data with parity. however, parity can be added only in 7-bit uart or 8-bit uart mode. with sccr1 register, even (odd) parity can be selected. for transmission, parity is automatically generated according to the data written in the transmission buffer scbuf, and data are transmitted after being stored in scbuf1 when in 7-bit uart mode while in scmod1 in 8-bit uart mode. and must be set before transmission data are written in the transmission buffer. for receiving, data are shifted in the receiving buffer 1, and parity is added after the data are transferred in the receiving buffer 2 (scbuf1), and then compared with of scbuf0 when in 7-bit uart mode and with sccr1 when in 8-bit uart mode. if they are not equal, a parity error occurs, and sccr1 ?g is set. error flag three error ?gs are provided to increase the reliability of receiving data. 1) overrun error (sccr1 ) if all bits of the next data are received in receiving buffer 1 while valid data are still stored in receiving buffer 2 (scbuf1), an overrun error will occur. 2) parity error (sccr1 ) the parity generated for the data shifted in receiving buffer 2 (scbuf1) is compared with the parity bit received from the rxd1 pin. if they are not equal, a parity error occurs. 3) framing error (sccr1 ) the stop bit of received data is sampled three times around the center. if the majority results is ?? a fram- ing error occurs. 11 generation timing 1) uart mode note: framing error occurs after an interrupt has occurred. therefore, to check for framing error during interrupt operation, it is necessary to wait for 1 bit period of time. receiving mode 9 bit 8 bit + parity 8 bit, 7 bit + parity, 7 bit interrupt timing center of last bit (bit 8) center of last bit (parity bit) center of stop bit framing error timing center of stop bit center of stop bit center of stop bit parity error timing center of last bit (bit 8) center of last bit (parity bit) center of stop bit over-run error timing center of last bit (bit 8) center of last bit (parity bit) center of stop bit transmitting mode 9 bit 8 bit + parity 8 bit, 7 bit + parity, 7 bit interrupt timing just before last bit is transmitted ??
122 toshiba corporation TMP90CM36 3.8.6 action explanation (1) mode 0 (i/o interface mode) this mode is used to increase the number of i/o pins of TMP90CM36 for transmitting or receiving data to or from the external shifter register. this mode includes sclk1 output mode to output synchronous clock sclk1 and sclk1 input mode to input external synchronous clock sclk1. figure 3.8 (15). i/o interface mode
toshiba corporation 123 TMP90CM36 transmission in sclk1 output mode, 8-bit data and synchronous clock are output from txd1 pin and slck1 pin, respectively, each time the cpu writes data in the transmission buffer. when all data is output, irf2 will be set to generate inttx interrupt. figure 3.8 (16). transmitting operation in i/o interface mode (sclk1 output mode) in sclk1 output mode, 8-bit data are output from txd1 pin when slck1 input becomes active while data are written in the transmission buffer by cpu. when all data are output, will be set to gen- erate inttx1 interrupt. figure 3.8 (17). transmitting operation in i/o interface mode (sclk1 input mode)
124 toshiba corporation TMP90CM36 receiving in sclk1 output mode, received data are read by the cpu, and synchronous clock is sclk1 pin and the next data are shifted in the receiving buffer 1 whenever the receive interrupt ?g irf2 is cleared. when 8-bit data are received, the data will be trans- ferred in the receiving buffer 2 (scbuf1), and will be set again to generate intrx1 inter- rupt. figure 3.8 (18). receiving operation in i/o interface mode (slck1 output mode) in sclk1 input mode, received data are read by the cpu, and the next data is shifted in the receiving buffer 1 when sclk1 input becomes active while the receive interrupt ?g is cleared. when 8-bit data is received, the data will be transferred in the receiving buffer 2 (scbuf1), and will be set again to generate intrx1 interrupt. figure 3.8 (19). receiving operation in i/o interface mode (slck input mode) for data reception, the system must be placed in the receive enable state (scmod1 = ??
toshiba corporation 125 TMP90CM36 (2) mode 1 (7-bit uart mode) 7-bit mode can be set by setting serial channel mode register scmod1 to ?1? in this mode, a parity bit can be added, and the addi- tion of a parity bit can be enabled or disabled by serial channel control register. sccr1 , and even parity or odd parity is selected by sccr1 when is set to ??(enable). setting example: when transmitting data with the fol- lowing format, the control registers should be set as described below.
126 toshiba corporation TMP90CM36 (3) mode 2 (8-bit uart mode) 8-bit uart mode can be speci?d by setting scmod1 to ?0? in this mode, a parity bit can be added, the addition of a parity bit is enabled or disabled by sccr1 , and even parity or odd parity is selected by sccr1 when is set to ??(enable). setting example: when receiving data with the follow- ing format, the control registers should be set as described below.
toshiba corporation 127 TMP90CM36 (4) mode 3 (9-bit uart mode) the 9-bit uart mode can be speci?d by setting scmod1 to ?1? in this mode, parity bit cannot be added. for transmission, the msb (9th bit) is written in scmod1 , while in receiving it is stored in sccr1 . for writing or reading the buffer, the msb is read or written ?st then scbuf1. w ake-up function in 9-bit uart mode, the wake-up function of slave controllers is enabled by setting scmod1 to ?? the interrupt intrx1 occurs only when sccr1 = 1. figure 3.8 (20). serial link using wake-up function
128 toshiba corporation TMP90CM36 protocol select the 9-bit uart mode for the master and slave controllers. set the scmod1 bit of each slave control- ler to ??to enable data receiving. a the master controller transmits one-frame, includ- ing the 8-bit select code of the slave controllers. the msb (bit 8) scmod1 is set to ?? ? each slave controller receives the above frame, and clears wu bit to ??if the above select code matches its own select code. ? the master controller transmits data to the specified slave controller whose scmod1 bit is cleared to ?? the msb (bit 8) scmod1 is set to ?? ? the other slave controllers (with scmod1 bit remaining at ?? ignore the receiving data because their msbs (bit 8 or sccr1 ) are set to ??to disable the interrupt intrx1. when the wu1 bit is cleared to ?? the interrupt intrx1 occurs, so that the slave controller can read the receiving data. the slave controllers (wu1 = 0) transmit data to the master controller, and it is possible to indicate the end of data receiving to the master controller by this transmission. setting example: to link two slave controllers seri- ally with the master controller, and use the internal clock ?1 (fc/2) as the transfer clock .
toshiba corporation 129 TMP90CM36
130 toshiba corporation TMP90CM36 3.8.7 con?uration the serial channels are connected to external circuits through three-pin serial ports: sclk2 (p76), txd2 (p77) and rxd2 (p75). figure 3.8 (21). block diagram of serial channels (sio2)
toshiba corporation 131 TMP90CM36 serial clock sio2 pulses make the following selections through the serial channel mode register scmod2. clock source selection selects either an internal or external clock as the clock source. a. (internal clock) scmod2 selects the speed of either ?1 (fc/4), ?1 (fc/8), ?4 (fc/32), or ?16 (fc/128) serial clock. the serial clock pulse is externally output from the sclk2 pin. the serial clock automatically stops after it ends the ?-frame?serial operation. it waits until next serial operation. b. (external clock) uses the clock pulse externally supplied to the sclk2 pin as the serial clock pulse. shift edge selection a. rising edge shift data shifts on the serial clock pulsess rising edge (falls at the sclk2 pin). b. falling edge shift data shifts on the serial clock pulsess falling edge (rises at the sclk2 pin or no falling edge shift in send mode)
132 toshiba corporation TMP90CM36 3.8.8 explanation of operations the send, receive and simultaneous send-receive modes for scmod2 . (1) send mode the ?st send data is written into buffer registers scbuf after the send mode is set in the command register. (data will not be written into the buffers if the command register is not in send mode.) then, storing ??into serial transfer control registers scmod2 starts the send. as the send starts, the send data is synchronized with serial clock pulses and sequentially output from the txd2 pin on the lsb side. at the same time, the send data is transferred from the buffer registers to the shift registers. since the buffer registers are empty, buffer empty interrupt inttx2 is generated to request the next send data. when the interrupt service program writes the next send data into the buffer register, the interrupt request signal isnt cleared to ?? (internal clock pulse) in the internal clock operations, if all data is sent and no subsequent data is stored in the register, the serial clock pulse stops and a wait begins. (external clock pulses) in the internal clock operation, data must be stored in the buffer registers before the next data shift operation begins. the transfer speed in an interrupt service pro- gram is determined by the maximum delay time from the interrupt request generation to buffer register data write. to end a send, the buffer empty interrupt service pro- gram disables (clears to ?? serial transfer control reg- ister scmod2 instead of writing the next send data. when serial transfer control is disabled, the serial transfer ends when the send data now being shifted out is ?ished being sent. the end of send can be determined by the status of serial transfer monitor ?g scmod2 . in the external clock operation, the serial transfer control reg- ister scmod2 must be disabled before start- ing the next send data shift operation. if the serial transfer control register scmod2 is not disabled before the shift operation begins, oper- ations stop after sending the next send data (dummy).
toshiba corporation 133 TMP90CM36 figure 3.8 (22). chart of serial channel 0 send mode timing
134 toshiba corporation TMP90CM36 (2) receive mode setting the command register to receive mode, then setting serial serial transfer control scmod2 to enable makes receive possible. shift data is syn- chronized with serial clock pulses and fetched from the rxd2 pin. when data is fetched, it is transferred from the shift register to the buffer register and the buffer-full interrupt intrx2 is generated to request a read of receive data. when the interrupt service program read the next receive data from the buffer register, the interrupt request signal is cleared. the following data continues to be fetched after the interrupt is generated. after the interrupt request is cleared, data is trans- ferred from the shift register to the buffer register when data is fetched. (internal clock pulses) in the internal clock operation, if the previous receive data has not been read from the buffer reg?ter after the next data is fetched, the serial clock stops and waits until the previous data is read. (external clock pulses) in the external operation, shift operations are synchro- nized with externally supplied clock pulses. the data is read before the next receive data is transferred into the buffer register. if the previous data has not been read, the receive data will not be transferred into the buffer registers and all subsequently input receive data will be cancelled. the maximum transfer speed of the external clock operation is determined by the maxi- mum delay time from interrupt request generation to receive data read. rising and falling edge shifts can be selected in the receive mode. because data is fetched on the serial clock pulsess rising edge in the rising edge shift, the ?st shift data must already be input to the rxd2 pin when the initial serial clock pulses are applied at trans- fer start. (3) send-receive mode the ?st send data is written into buffer registers scbuf2 after the send-receive mode is set by the command register. setting the serial transfer control register scmod2 to 1 enables receiving or sending data. send data is output from the txd2 pin on the rising edge of the serial clock pulse, while receive data is fetched from the rxd2 pin on the falling edge of the serial clock pulse. when data is fetched, data is transferred from the shift registers to the buffer registers and buffer-full interrupt intrx2 is genrated to request receive data read. when the interrupt service program reads the next receive data from the buffer register, the interrupt request signal is cleared. (internal clock pulses) in the internal clock operation, a wait begins until the received data is read and the next send data is written. (external clock pulses) in the external clock operation, the receive data must be read and the next send data written before starting the next shift operation, because the shift operation is synchronized with the external supplied clock pulses. the maximum transfer speed of the external clock operation is determined by the maximum delay time from interrupt request generation to send data fetch and receive data write. because the same buffer registers are used for send and receive, always ensure that send data is written after 8 bits of receive data are fetched. to end send-receive, disable the serial transfer control register. when the serial transfer control register is dis- abled, send-receive ends afetr receive data is orga- nized and transferred to the buffer register. the program checks the end of send-receive by read- ing serial transfer monitor ?gs scmod2 .
toshiba corporation 135 TMP90CM36 figure 3.8 (23) - 1. chart of serial channel ?send-receive mode (falling edge shift) timing
136 toshiba corporation TMP90CM36 figure 3.8 (23) - 2. chart of serial channel ?send-receive mode (falling edge shift) timing
toshiba corporation 137 TMP90CM36 figure 3.8 (24) - 1. serial channel control register
138 toshiba corporation TMP90CM36 figure 3.8 (24) - 2. serial channel buffer registers
toshiba corporation 139 TMP90CM36 3.9 time base counter (tbc) the TMP90CM36 has a 20-bit time base counter. this time base counter can select from the fundamental clock (fc) divided by 2, it divided by 3 or external input clock (exin). the various outputs of this time base timer are used as reference signals for 24-bit capture and timing pulse generator (tpg). the contents of the time base counter can be read with registers tbcd0 and tbcd1. interrupts can be generated from the tbc11 ~ tbc20 output signals of the time base counter. when an int tb interrupt has been generated, it is possi- ble to determine whether the interrupt generation destination is inttbc1 or inttbc2 by reading cfreg . table 3.9 (1) time base counter and cycle figure 3.9 (1). time base counter (tbc) block diagram
140 toshiba corporation TMP90CM36 figure 3.9 (2). time base counter mode register (tbmod)
toshiba corporation 141 TMP90CM36 figure 3.9 (3). time base counter related register
142 toshiba corporation TMP90CM36 3.10 timing pulse generators (tpg) the TMP90CM36 has a built-in 2 channels 24-bit x 4-stage timing pulse generation circuit with fifo (tpg0, tpg1) that are used to control the various signals and mechanical parts. timing pulse generators (tpg) generate timing pulses that are synchronized with the time base counter (tbc) and which have an accuracy of 640ns (@ fc - 12.5mhz). figure 3.10 (1). tbg0 block diagram
toshiba corporation 143 TMP90CM36 3.10.1 operation tpg0 1) data tpg0 has a total of 2 bits and 4 stages of fifo: 6 bits in the output data register tpgreg0 and 16 bits in the comparator data registers tpgd00 and tpgd01. the value written to the output data register is output when the values written to the comparator data regis- ters and the tbc3 - tbc18, the tbc4 ~ tbc19 or the tbc5 ~ tbc20 values match. writing data to the tpgreg0 byte of the data regis- ters increments the fifo address. thus, write data to memory addresses tpgd00, tpgd01, and tpgreg0, in that order. 2) fifo tpg0 has 4-stage fifo (first in first out) circuit. this fifo generates an interrupt signal when the data becomes empty. this interrupt signal is not generated after a reset or tp reset. once data have been written to the data register and fifo has been incremented, an interrupt is gener- ated when data written to the output data register is output and fifo becomes empty. the interrupt is controlled with tpcreg0 . 3) tp reset the cfreg register resets tpg0. writing ??to this register resets the following tpg0 circuits. fifo address counter fifo status a empty interrupt flag note: the tpg0 output buffer is not reset; therefore, the previous tp value is retained. this buffer is cleared to ?? however, by sys- tem resets. ?tpg1 tpg1 operate the same tpg0.
144 toshiba corporation TMP90CM36 3.10.2 control register figure 3.10 (2) - 1. tpg0, tgp1 related registers
toshiba corporation 145 TMP90CM36 figure 3.10 (2) - 2. tpg0, tgp1 related registers
146 toshiba corporation TMP90CM36 figure 3.10 (2) - 3. tpg0, tgp1 related registers
toshiba corporation 147 TMP90CM36 figure 3.10 (2) - 4. tpg0, tgp1 related registers
148 toshiba corporation TMP90CM36 3.11 capture circuit the TMP90CM36 has a ram with 24-bits, 4-step fifo to simplify various time measurements. the time (20-bit data from tbc1 - tbc20) is written in real time together with the input data in ram by the servo input signals. the latch is operated and intcap interrupts to the cpu are generated bu the input signals. figure 3.11 (1) is a block diagram of the capture circuit. figure 3.11 (1). block diagram of capture circuit
toshiba corporation 149 TMP90CM36 3.11.1 explanation of operations 1) capture there are 4 input sources for the capture circuit: cap0, cap1, cap2, cap3 (vp) signals. a total 24 bits, the 4 input signal bits and the 20-bit values from the time base counter (tbc1 - tbc20) to the 3 bytes at capreg0 ~ 2 are latched using the input signal edge (select the rising-edge or the falling-edge). the 24-bit data is obtained by reading the data* at the addresses in the sequence capreg0, capreg1 and capreg2. note: *this address must always be read last because reading the data at address capreg2 shifts the fifo address. 2) fifo because this capture circuit uses the fifo (first in first out) method, it always reads the data that is latched ?st. if the 4-step fifo contents are full, the capture operation is disabled by the input signal. the fifo sta- tus register (capfst) will be ffh when this happens. when the capfst is 00h, ffh is read out when cap- ture data is read out. always read the capture data out when the fifo status register is not ??or after the intcap interrupt is generated. 3) cap reset the capture circuit has a software reset in addition to its system reset. writing ??into the cfpreg < cafrs> resets the fol- lowing circuits: fifo address counter fifo status
150 toshiba corporation TMP90CM36 3.11.2 control registers figure 3.11 (2). capture related register
toshiba corporation 151 TMP90CM36 3.12 pwm (pulse width modulation) output the TMP90CM36 has 2 built-in channels for outputting pulse width modulation (pwm). d/a conversion output can be obtained by attaching an external low-pass ?ter for simple motor control. one cycle in 12-bit resolution pwm output is tm = 212/ (fc/2) [seconds]. upper 7-bit pwm data latch data control pulse width for the carrier frequency in time ts (ts = tm/ 32)[seconds]. when the upper 7-bit data is n (n = 0 to 128), the low level pulse width is n*t (t = 2/(fc/2)) with ts as the cycle. the lower 5-bit data controls the applied pulses of width t in ?2?time periods ts (i) (i = 0 - 31) within the tm cycle. the low level pulse width is (n + 1) *t in the period in which applied pulses are output. figure 3.12 (1)
152 toshiba corporation TMP90CM36 figure 3.12 (2). block diagram of pw0 and pw1
toshiba corporation 153 TMP90CM36 3.12.1 control register figure 3.12 (3) - 1. pwm related register
154 toshiba corporation TMP90CM36 figure 3.12 (3) - 2. pwm related register
toshiba corporation 155 TMP90CM36 3.13 analog/digital converter TMP90CM36 contains a high-speed, high-accuracy analog/ digital converter (a/d converter) with 8-channel analog input that features 8-bit sequential comparison. figure 3.13 (1) shows the block diagram of the a/d con- verter. 8-channel analog input pins (an7 to an0) are shared by input-only port p6 and so can be used as input port. figure 3.13 (1). block diagram of a/d converter
156 toshiba corporation TMP90CM36 3.13.1 control registers figure 3.13 (2). a/d conversion mode register (admod)
toshiba corporation 157 TMP90CM36 figure 3.13 (3). a/d conversion result register (adreg0 ~ 3) figure 3.13 (4). a/d converter channel select register
158 toshiba corporation TMP90CM36 3.13. 2 operation (1) analog reference voltage high analog reference voltage is applied to the avcc pin, and the low analog voltage is applied to avss pin. the reference voltage between avcc and avss is divided by 256 using ladder resistance, and compared with the analog input voltage for a/d conversion. (2) analog input channels analog input channel is selected by admod , admod . however, which channel to select depends on the operation mode of the a/d converter. in ?ed analog input mode, one channel is selected by admod , admod among three pins: an0 to an3. in analog input channel scan mode, the number of channels to be scanned from an0 is speci?d by admod , admod , such as an0 ? an1, an0 ? an1 ? an2, and an0 ? an1 ? an2 ? an3 or the number of channels to be scanned from an4 is such as an4 ? an5, an4 ? an5 ? an6, an4 ? an5 ? an6 ? an7. when reset, a/d conversion channel register will be initialized to admod = 00, adch = 0 so that an0 pin will be selected. the pins which are not used as analog input channel can be used as ordinary input port p5. (3) starting a/d conversion a/d conversion starts when a/d conversion register admod is written ?? when a/d conversion starts, a/d conversion busy ?g admod which indicates ?/d conversion is in progress?will be set to ?? (4) a/d conversion mode both ?ed a/d conversion channel mode and a/d conversion channel scan mode have two conversion modes, i.e., single and repeat conversion modes. in ?ed channel repeat mode, conversion of speci?d one channel is executed repeatedly. in scan repeat mode, scanning from an0 ? an3 or from an4, ? an7 is executed repeatedly. a/d conversion mode is selected by admod . (5) a/d conversion speed selection there are two a/d conversion speed modes: high speed mode and low speed mode. the selection is executed by admod register. when reset, admod will be initialized to ?? so that high speed conversion mode will be selected.
toshiba corporation 159 TMP90CM36
160 toshiba corporation TMP90CM36 (6) a/d conversion end and interrupt a/d conversion single mode admod for a/d conversion end will be set to ?? admod ?g will be reset to ?? and intad interrupt will be enabled when a/d conversion of speci?d channel ends in ?ed conversion channel mode or when a/d conversion of the last channel ends in channel scan mode. interrupt requesting ?p-?p is cleared only by resetting operation or reading the a/d conversion result storing register and cannot be cleared by instruction. a/d conversion repeat mode for both ?ed conversion mode and conversion chan- nel scan mode, intad will be disabled when in repeat mode. always leave the inte0 ?g at ?? write ??to admod to end the repeat mode. then, the repeat mode will be exited as soon as the conversion in progress is completed. (7) storing the a/d conversion result the results of a/d conversion are stored adreg04 to adreg37 registers for each channel. in repeat mode, the registers are updated whenever conversion ends. adreg04 to adreg37 are read-only registers. (8) reading the a/d conversion result the results of a/d conversion are stored adreg04 to adreg37 registers. when the contents of one of adreg0 to adreg3 registers are read, admod will be cleared to ?? setting example: when the analog input volt- age of the an3 pin pin is a/ d converted and the results are read in the memory at ff10h by a/d interrupt intad routine.
toshiba corporation 161 TMP90CM36 3.14 8-bit power supply voltage model d/a converter the TMP90CM36 contains 8-bit resolution d/a voltage with the following merit. TMP90CM36 contains 2 channel in the 8-bit resolution d/a converter (r-2r formula) analog voltage v which done output is decided setting val- ues in register dareg0, dareg1. figure 3.14 (1) shows the block diagram of d/a converter. figure 3.14 (1). d/a converter block diagram
162 toshiba corporation TMP90CM36 figure 3.14 (2). d/a converter related register
toshiba corporation 163 TMP90CM36 3.14.1 operation if built-in d/a converter is d/a converter drive register dadrv to ?? d/a converter conversion register dareg1, dareg0 changes values from digital to analog, and then it is output in conversion voltage from d-a1, d-a0 pin. relate input data with output voltage shows figure 3.14 (2). reset operations is reset to ?? from d-a1, d-a0 pin is output ?v?also both dareg1 and dareg0 is reset ?0h? therefore, if it set dadrv to ??after reset, it will output ?vcc/4?(explanation of figure 3.14). when d/a converter is in use, register write dadrv to ??the using channel. future, if it write input data in the dareg, it is output applicability analog values. moreover, if it is practice halt order after nomination in the stop mode (wdmod = 0,1), from d-a0, d-a1 pin without relation values dadrv, dareg is output ?v?
164 toshiba corporation TMP90CM36 3.15 watchdog timer (looping detection timer) the purpose of the watchdog timer (wdt) is to detect the start of cpu misoperation due to noise, etc., and bring it back to normal. 3.15.1 con?uration the TMP90CM36f multiplexes the watchdog timer output (wdtout ) and p80 (pin 30). p80 (output port) is switched to the wdtout pin and reset is returned inside the chip by setting bit wdmod = ??of the watchdog timer mode register at address #ffd0h to ?? figure 3.15 (1) shows the wdt block diagram. figure 3.15 (1). watchdog timer block diagram
toshiba corporation 165 TMP90CM36 the watchdog timer is a 22-stage binary counter that uses (fc/2) as the input clock. the binary counter outputs are 2 16 /fc, 2 18 /fc, 2 20 /fc and 2 22 /fc. one of these outputs is used for watchdog timer output wdtout . wdtout outputs ??to reset the peripheral devices when the watchdog timer over?ws. wdtout also is connected to reset inside the wdtout TMP90CM36. in this case, wdtout outputs ??in a 32/fxtal = 2.0 m sec (fxtal = 16mhz) cycle and simultaneously resets the TMP90CM36. 3.15.2 control registers the watchdog timer (wdt) is controlled by two control registers (wdmode and wdcr). (1) watchdog timer mode register (wdmod watchdog timer detection time setting (wdtp) this is a 2-bit ?g used to set the watchdog timer interrupt time for looping (runaway) detection. this ?g is initialized to wdmod = 00 by resets, which results in a value of 216/fc [sec]. (the number of states is approximately 32.768.) watchdog timer enable/disable control (wdte) this bit is initialized to wdte = 1 by resets, which enables the watchdog timer. to disable the watchdog timer, it is only necessary to clear this bit to ??and write the disable code (b1h) to the wdcr register. it is dif?ult for the watchdog timer to be disabled by looping. to disable the watchdog timer after it has been enabled, it is only necessary to write ??to the bit. a watchdog timer out reset connection (rescr) this ?g is used to set whether or not the TMP90CM36 will be reset when looping is detected and whether or not to output wdtout . is set to ??by reset operations; therefore, pin 30 is set as the wdtout pin and connected inter- nally to the reset pin. pin 30 can be set as either the wdtout pin or port pin by overwriting . however, caution is required because a redundant structure is used to pre- vent misoperation. the bit is linked to the p38cr therefore, it is always necessary to write ??the when the bit is overwritten. the bit is set only after ??is written to the and then either ??or ??is written to the rescr bit. writing to the bit automatically clears the to ?? therefore, when resetting the bit, again write ??to the .
166 toshiba corporation TMP90CM36 figure 3.15 (2). flowchart of p80/wdtout pin switching
toshiba corporation 167 TMP90CM36 figure 3.15 (3). watchdog timer mode register
168 toshiba corporation TMP90CM36 (2) watchdog timer control register (wdcr) this register enables and disables the watchdog timer, and clears the binary counter. disable control the watch timer is disabled by clearing wdmod to ??and then writing the disable code (b1h) to the wdcr register. enable control set wdmod to ?? binary counter clear control the binary counter is cleared and restarts counting when the clear code (4eh) is written to wdcr. figure 3.15 (4). watchdog timer control register
toshiba corporation 169 TMP90CM36 3.15.3 operation the watchdog timer is a timer that outputs ??level from the watchdog timer output pin (wdtout ) after the detection time set with wdmod elapses. the watchdog timer binary counter is cleared to ??before an over?w occurs. if the cpu misoperates (loops) due to noise, etc., the binary counter will over?w unless the parity counter clear instruction is executed. the cpu can be returned to normal operation by resetting internally. a reset can be applied to both the TMP90CM36 and cpu by connecting the wdtout pin to the reset pins of the peripheral devices. the watchdog timer again starts operating immediately after the reset is canceled. the watchdog timer stops during the idle mode and stop mode and operates during the run mode. the watch- dog timer can also be disabled when entering the run mode.
170 toshiba corporation TMP90CM36 4. electrical characteristics TMP90CM36f/TMP90CM36t note: i dar is guaranteed for up to 8 optional ports. 4.1 maximum ratings symbol item rating unit v cc power supply voltage -0.5 ~ + 7 v v in input voltage -0.5 ~ v cc + 0.5 v ? iol output current (total) 100 ma ? ioh output current (total) -70 ma p d power dissipation (ta = 85 c) f 500 mw t 600 t solder soldering temperature (10sec) 260 t stg storage temperature -65 ~ 150 c t opr operating temperature -20 ~ 70 c 4.2 dc electrical characteristics v cc = 5v 10%, ta = -20 ~ 70 c (1 ~ 16mhz) typical values are for ta = 25 c, v cc = 5v. symbol item min max unit conditions v il input low voltage (p0) -0.3 0.8 v v il1 p1, p2, p3, p4 , p5, p5, p6, p7 -0.3 0.3v cc v v il2 reset , p81 (int0), p82 (stby ) -0.3 0.25v cc v v il3 ea -0.3 0.3 v v il4 x1 -0.3 0.2v cc v v ih input high voltage (p0) 2.2 v cc + 0.3 v v ih1 p1, p2, p3, p4 , p5, p5, p6, p7 0.7v cc v cc + 0.3 v v ih2 reset , p81 (int0), p82 (stby ) 0.75v cc v cc + 0.3 v v ih3 ea v cc - 0.3 v cc + 0.3 v v ih4 x1 0.8v cc v cc + 0.3 v v ol output low voltage 0.45 v i ol = 1.6ma v oh v oh1 v oh2 output high voltage 2.4 0.75v cc 0.9v cc v v v i oh = -400 m a i oh = -100 m a i oh = -20 m a i dar darlington drive current (8 i/o pins max) -1.0 -3.5 ma v ext = 1.5v r ext = 1.1k w i li input leakage current 0.02 (typ) 5 m a 0.0 vin v cc i lo output leakage current 0.05 (typ) 10 m a 0.2 vin v cc - 0.2 i cc operating current (run) idle 35 (typ) 1.5 (typ) 50 5 ma ma t osc = 16mhz stop (ta = -20 ~ 70 c) stop (ta = 0 ~ 50 c) 0.2 (typ) 40 10 m a m a 0.2 vin v cc - 0.2 v stop power down voltage of (@stop) (ram back up) 2.0 6.0 v v il1 = 0.2vcc, v il2 = 0.8vcc r rst reset pull up register 50 150 k w cio pin capacitance 10 pf testfreq = 1mhz v th schmitt width (reset , p81, p82) 0.4 1.0 (typ) v
toshiba corporation 171 TMP90CM36 ac measuring conditions output level: high 2.2v/low 0.8v,c l = 50pf (however, cl = 100pf for ad0 ~ 7, a8 ~ 15, ale, rd , wr ) input level high 2.4v/low 0.45v (d0 ~ d7) high 0.8v cc /low 0.2v cc (excluding ad0 ~ ad7) 4.3 ac electrical characteristics v cc = 5v 10% ta = -20 ~ 70 c (1 ~ 16mhz) symbol item variable 12.5mhz clock 16mhz clock unit min max min max min max t osc oscillation cycle ( = x) 62.5 1000 80 62.5 ns t al a0 ~ a7 effective address ? ale fall 0.5x - 15 25 16 ns t la ale fall ? a0 ~ a7 hold 0.5x - 15 25 16 ns t ll ale pulse width x - 40 40 23 ns t lc ale fall ? rd /wr fall 0.5x - 30 10 1 ns t cl rd /wr rise ? ale rise 0.5x - 20 20 11 ns t acl a0 ~ a7 effective address ? rd /wr fall x - 25 55 38 ns t ach upper effective address ? rd /wr fall 1.5x - 50 70 44 ns t ca rd /wr fall ? upper address hold 0.5x - 20 20 11 ns t adl a0 ~ a7 effective address ? effective data input 3.0x - 35 205 153 ns t adh upper effective address ? effective data input 3.5x - 55 225 164 ns t rd rd fall ? effective data input 2.0x - 50 110 75 ns t rr rd pulse width 2.0x - 40 120 85 ns t hr rd rise ? data hold 0 0 0 ns t rae rd rise ? address enable x - 15 65 48 ns t ww wr pulse width 2.0x - 40 120 85 ns t dw effective data ? wr rise 2.0x - 50 100 65 ns t wd wr rise ? effective data hold 0.5x - 10 30 21 ns
172 toshiba corporation TMP90CM36 4.4 a/d conversion characteristics v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol parameter condition min max unit avcc analog reference voltage vcc - 1.5 vcc vcc v a gnd analog reference voltage vss vss vss v ain analog input voltage range vss vcc i ref analog reference voltage power supply current 0.5 1.0 ma error (quantize error of 0.5 lsb not included) total error (ta = 25 c, vcc = v ref = 5.0v) 1.0 lsb total error 2.5 4.5 timer/counter input clock (ti2, ti4) v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol item variable 12.5mhz clock 16mhz clock unit min max min max min max t vck clock cycle 8x + 100 740 600 ns t vckl low clock pulse width 4x + 40 360 290 ns t vckh high clock pulse width 4x + 40 360 290 ns 4.6 interrupt operation v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol item variable 12.5mhz clock 16mhz clock unit min max min max min max t intal int0 low level pulse width 4x 320 250 ns t intah int0 high level pulse width 4x 320 250 ns t intbl int1, int2 low level pulse width 8x + 100 740 600 ns t intbh int1, int2 high level pulse width 8x + 100 740 600 ns
toshiba corporation 173 TMP90CM36 4.7 d/a conversion characteristics (vcc = 5v, vss = avss = 0v) (2) sclk1 output mode v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol item min typ max unit analysis ability 8 bits absoluteness accuracy (vcc = avcc = 5v) 1.0 % t su establishment time 3 m s r o output resistance 1 2 4 k w v avss analog power supply voltage 0 v v davref analog power supply voltage 4 v cc v i davref reference power supply input current 0 2.5 5 ma 4.8 serial channel sio1 timing - i/o interface mode (1) sclk1 input mode v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol item variable 12.5mhz clock 16mhz clock unit min max min max min max t scy sclk1 cycle 16x 1.28 1 m s t oss output data ? rising edge of sclk t scy /2 - 5x - 50 190 137 ns t ohs sclk1 rising edge ? output data hold 5x - 100 300 212 ns t hsr sclk1 rising edge ? input data hold 0 0?ns t srd sclk1 rising edge ? effective data input t scy - 5x - 100 780 587 ns symbol parameter variable 12.5mhz clock 16mhz clock unit min max min max min max t scy sclk cycle (programmable) 16x 8192x 1.28 655.4 1 512 m s t oss output data setup ? sclk rising edge t scy - 2x - 50 970 725 ns t ohs sclk rising edge ? output data hold 2x - 80 80 45 ns t hsr sclk rising edge ? input data hold 0 0?ns t srd sclk rising edge ? effective data input t scy - 2x - 150 970 725 ns
174 toshiba corporation TMP90CM36 4.9 serial channel sio2 timing v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol item condition 10mhz clock variableclock unit min max min max t scr serial port clock cycle time internal 800 12800 8x 128x ns external 1600 16x t scl sclk2 low width internal **** ns external **** t sch sclk2 high width internal **** ns external **** t skdo sclk2 ? txd2 (output data) delay time internal *? ns external *? t srd sclk2 rising edge to input data valid internal *? ns external *? t hsr input data hold after sclk2 rising edge internal *? ns external *?
toshiba corporation 175 TMP90CM36 4.10 timing chart
176 toshiba corporation TMP90CM36 4.11 serial channel sio1 i/o interface mode timing chart 4.12 serial channel sio2 timing chart
toshiba corporation 177 TMP90CM36 5. special function register list the special function registers (sfr) are the input/output ports, peripheral control registers. these sfr are assigned to 96- byte address areas from 0ffa0h to 0ffffh. (1) input/output port (2) input/output port control (3) timer/event counter control (4) a/d converter control (5) interrupt control (6) hdma control (7) wdt control (8) serial channel control (9) time base counter control (10) timing pulse generation control (11) capture control (12) d/a converter (13) pwm control
178 toshiba corporation TMP90CM36 TMP90CM36 special function register list
toshiba corporation 179 TMP90CM36 (1) i/o port
180 toshiba corporation TMP90CM36 (2) i/o port control (1/2)
toshiba corporation 181 TMP90CM36 (2) i/o port control (2/2)
182 toshiba corporation TMP90CM36 (3) timer/event counter control (1/3)
toshiba corporation 183 TMP90CM36 (3) timer/event counter control (2/3)
184 toshiba corporation TMP90CM36 (3) timer/event counter control (3/3)
toshiba corporation 185 TMP90CM36 (4) a/d converter control
186 toshiba corporation TMP90CM36 (5) interrupt control
toshiba corporation 187 TMP90CM36 (6) hda control (7) wdt control
188 toshiba corporation TMP90CM36 (8) serial channel control (1/2)
toshiba corporation 189 TMP90CM36 (8) serial channel control (2/2)
190 toshiba corporation TMP90CM36 (9) time base counter control
toshiba corporation 191 TMP90CM36 (10) timing pulse generators control (1/2)
192 toshiba corporation TMP90CM36 (10) timing pulse generators control (2/2)
toshiba corporation 193 TMP90CM36 (11) capture control
194 toshiba corporation TMP90CM36 (12) d/a converter (13) pwm control

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Price & Availability of TMP90CM36

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